"Arteris’ FlexNoC interconnect IP products automatically generate SystemC TLM models for SoC architectural exploration. FlexNoC’s integration with Platform Architect enables users to perform realistic and sophisticated analysis of complete SoC simulations in a simple and seamless manner."
- Kurt Shuler, Director of Marketing at Arteris
Arteris FlexNoC Network on Chip (NoC) Interconnect IP improves performance, power consumption and die size of system on chip (SoC) devices for consumer electronics, mobile, automotive and other applications.
Using FlexNoC solves customer pain. Traditional bus and crossbar interconnect approaches create serious problems for architects, digital and physical designers, and integrators: Massive numbers of wires, increased heat and power consumption, failed timing closure, spaghetti-like routing congestion leading to increased die area, and difficulty making changes for derivatives.
Whether using AXI, OCP, AHB or a proprietary protocol, Arteris FlexNoC Network on Chip (NoC) IP reduces the number of wires by nearly one half, resulting in fewer gates and a more compact chip floor plan. Having the option to configure each connection’s width, and each transaction’s dynamic priority, assures meeting latency and bandwidth requirements. And with the Arteris FlexNoC IP configuration tool suite, design and verification can be done easily, in a matter of days or even hours.
Arteris invented Network on Chip technology, offering the world’s first commercial solution in 2006. Arteris connects the IP blocks in semiconductors from Qualcomm, Samsung, TI, and others, representing over 50 System on Chip devices. Find out more about Arteris products at www.arteris.com.
Arteris FlexNoC’s automated interconnect IP generator creates SystemC TLM 2.0 loosely timed (LT), approximately-timed (AT) and cycle-timed (CT) models for the purpose of architectural exploration from within the FlexNoC IP generator. With this integration, Platform Architect imports these models automatically, completing port connections and enabling the tracing of transactions during SoC simulation.
This integration allows the user to more simply create a Platform Architect simulation model of the entire SoC, including the interconnect. Furthermore, as the interconnect design changes during SoC integration, the user can quickly measure the performance impacts on the SoC.