|Customer Case Studies: Fast and Predictable Implementation of Functional ECOs|
Functional ECOs bring uncertainty to the design schedule. This webinar highlights four different customer case studies on how to quickly and predictably implement functional ECOs using Formality Ultra.
Paul Usher, AC, Synopsys
Oct 13, 2016
|Identifying and Resolving Low Power Issues Before Tapeout|
This webinar highlights how to find low power issues during verification using Formality.
Bob Hatt, Staff Corporate Applications Engineer, Synopsys
Sep 29, 2015
|Identifying and Resolving Low Power Issues Before Tapeout - Traditional Chinese|
This webinar highlights how to find low power issues during verification using Formality. - Traditional Chinese
Richard Su, Staff AC, Synopsys
Sep 29, 2015
|STMicroelectronics: Successful Last-minute Functional ECO Implementation with Formality Ultra|
STMicroelectronics describes how they used Formality® Ultra to meet their tight release schedule for their ARM® core based designs despite having to implement multiple functional ECOs late.
Kailash Digari, Group Manager CPU-GPU design, STMicroelectronics; John Lehman, Senior CAE Manager, Synopsys
Feb 05, 2015
|Using ESP-CV for Faster Redundancy Verification in Memory Designs|
Learn how ESP-CV performs functional equivalence checks between a Verilog design and its transistor level implementation.
Dave Hedges, CAE, Implementation Group, Synopsys; Clay McDonald , R&D Manager, Implementation Group, Synopsys
Jan 19, 2011