Synopsys Formality White Papers

Formality® Introduces Combinational Equivalence Checking for Retimed Designs

Equivalency checking is an important and necessary step to verify the functional correctness of a design's implementation. However, conducting retiming during design implementation often made functional verification impossible. This paper discusses the specific verification challenges of retimed design verification and a new technology deployed by Synopsys that extends the reach of equivalence checking to include previously unsolvable retimed designs.

Synopsys is pleased to make available to its customers and prospective customers a paper that discusses new technology focused on solving this challenge, free of charge.

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1.

What is your current interest in Equivalence Checking?



2.

What is the most important aspect of an equivalence checking tool?
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3.

Which RTL language will most likely be used on your next design?



4.

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5.

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