Synopsys Formality White Papers

A Safe Approach to Hierarchical UPF Verification in Formality

Formality includes an intuitive, flow-based user interface to streamline the verification process. The IEEE-1801 I EEE Standard for Design and Verification of Low Power Integrated Circuits (UPF) adds additional constraints on the design affecting synthesis and verification. This paper describes how using Formality with the proper methodology can ensure that a hierarchical bottom verification flow will find design modifications which cause unwanted changes in behavior.

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1.	What is your current interest in Equivalence Checking?
	Current technology user Investigating for future use Just curious
2.	What is the most important aspect of an equivalence checking tool? (Check all that apply)
	Verification run time Capacity Ease of setup to ensure first-pass results Debug of real design differences Language compliance with synthesis tools Advanced arithmetic verification Retiming verification Verification of ECOs Other, please specify:
3.	Which RTL language will most likely be used on your next design?
	VHDL Verilog SystemVerilog
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