A Safe Approach to Hierarchical UPF Verification in Formality
Formality includes an intuitive, flow-based user interface to streamline the verification process. The IEEE-1801 I EEE Standard for Design and Verification of Low Power Integrated Circuits (UPF) adds additional constraints on the design affecting synthesis and verification. This paper describes how using Formality with the proper methodology can ensure that a hierarchical bottom verification flow will find design modifications which cause unwanted changes in behavior.
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