Synopsys Formality White Papers

A Safe Approach to Hierarchical UPF Verification in Formality

Formality includes an intuitive, flow-based user interface to streamline the verification process. The IEEE-1801 I EEE Standard for Design and Verification of Low Power Integrated Circuits (UPF) adds additional constraints on the design affecting synthesis and verification. This paper describes how using Formality with the proper methodology can ensure that a hierarchical bottom verification flow will find design modifications which cause unwanted changes in behavior.

Please complete the following form then click 'continue >>'.

Required Required Fields

Business Email:Required
First Name:Required
Last Name:Required
Phone:Required
Job Title:Required
Company:Required
Division:Optional
Country:Required
Address:Required
City:Required
State/Province:
Optional
Postal/Zip Code:Required

1.

What is your current interest in Equivalence Checking?



2.

What is the most important aspect of an equivalence checking tool?
(Check all that apply)









3.

Which RTL language will most likely be used on your next design?



4.

How would you best describe your role?









5.

Do you want to be contacted to learn more about Formality?



(requires browser cookies to be enabled)