Verification Debug Datasheet Download

Verdi Power-Aware Debug

Energy efficiency is a critical requirement in today's SoC designs and has necessitated the use of low power design techniques such as power gating, state retention, voltage islands and dynamic voltage/frequency scaling. These techniques introduce new dimensions to the design which exponentially increase the complexity of low power verification and demand a specialized power-aware debug solution. Easy and efficient low power debug needs to have a unified view of the design and its power intent, and an understanding and awareness of the impact of power intent on the design, in order to identify potential design-killing bugs early in the design flow.

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