Synopsys Verification IP for SATA
The Serial ATA (SATA) System Verification Component (SVC) is designed to verify SATA-based designs using both random and directed simulation. The SATA SVC supports constrained randomization parameters throughout the layers to aid in achieving coverage during verification. The SVC is verification methodology neutral, and can be integrated with and controlled by any hardwre verification language (e.g. SystemVerilog, UVM, C / C++, Vera, Specman, or Verilog). The SATA SVC supports all major simulators.