Timing closure is a critical step in the chip development process. The performance and timing of a design must be verified, and any violations must be investigated and resolved. This includes the specification and verification of timing exceptions. This white paper focuses on false paths and multi-cycle paths, the use of Synopsys Design Constraints (SDC) to specify these exceptions, and the “shift left” of verification from full-timing gate-level simulation to SDC-aware RTL simulation much earlier in the development process. This solution scales to cover even the largest and most complex system-on-chip (SoC) designs.