This whitepaper is designed to provide an understanding of how to build a DO-254 compliant ASIC/FPGA verification flow using the productivity enhancing features Verification Planner and Universal Report Generator which are found in Synopsys VCS®. The paper explains how differentiating tool features can be used to enhance and facilitate critical stages of the DO-254 verification process. The intended audience is designers and verifiers who are implementing high-reliability mission-critical systems, not limited to the civilian aerospace domain mandated by the RTCA DO-254.
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