Five Vital Steps to a Robust Testbench with DesignWare Verification IP and the Verification Methodology Manual for SystemVerilog
Traditionally, designers have used directed testing to meet their verification objectives, but this methodology is running out of steam. Designers are turning to advanced verification methodology standards built around techniques such as constrained random verification and functional coverage. This paper discusses advanced verification techniques using DesignWare Verification IP and Synopsys' Reference Verification Methodology (RVM), all of which can be used in testbenches based on the Verification Methodology Manual (VMM) for SystemVerilog.
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