White Paper: Improve SoC Design Productivity By Performing Quality Checks on IP Timing Constraints
When combining intellectual property (IP) blocks from various sources, the chip-level implementation teams may not have the detailed IP knowledge required to develop timing constraints for the IP. (In this context, IP” is used in the broader sense, referring to both external and internal sources of design blocks to be integrated into an SoC.) The team must therefore use timing constraints from the providers of the IP, and these constraints vary greatly in their quality.
Although much effort has gone into determining best practices for integrating IP blocks into an SoC design, the effort involved in integrating stand-alone block-level timing constraints into the chip-level timing environment is often overlooked. Because inadequate timing constraints can impose a significant barrier on design productivity for any type of design methodology, it is essential to get a complete, high-quality set of constraints to support predictable timing closure and signoff.
This paper describes quality checks and techniques for qualifying constraints, including checks for whether the IP is fully constrained, the quality of timing values, and the validity of timing exceptions. These techniques combine industry practices with experience from numerous designs completed by Synopsys Professional Services.
Click here to see an outline.