Hierarchical design flows offer many benefits that can result in improved productivity when designing complex digital chips. Depending on specific design goals, hierarchical design practices and techniques are especially important in managing design constraints and static timing analysis (STA), but the effects of hierarchical design must also be considered in tasks such as static crosstalk analysis, clock-tree synthesis and design for test. As chip complexity continues to grow, these techniques become increasingly important.
Developed by Synopsys Professional Services, this whitepaper describes proven techniques in hierarchical SoC design and discusses design methodologies in SoC integration that enable predictability in design completion.
Synopsys is pleased to make available to its customers and prospective customers this paper, free of charge. Click here to view an outline of the paper.