Save Up to 50% Dynamic Power on a GHz+ MIPS Core Implementation
Dynamic power saving is a major challenge today for both mobile and wired applications with latest tools and technology processes/nodes. There are various options and factors to be considered for synthesizable or soft Intellectual Property (IP) designs. The same IP may be used in a wide variety of applications with different requirements across various sub-micron technologies. Also with advanced technologies based tools and flows, it adds another dimension of problems to be considered. The performance/area to power trade-offs varies from technology to technology. Also depends on customer implementation requirements. This paper evaluates various options from available sub-micron technologies, specifically 28nm and Synopsys tools and flow perspective.
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