Today's FPGAs implement the equivalent of millions of ASIC gates and continue to grow in size and complexity. When the design fails to synthesize or fails to operate as expected on the board, the designer is faced with the daunting task of determining the source of the failure from among potentially thousands of RTL and constraint source files, many of which have been authored by another designer. Given how lengthy design iteration runtimes have become, today's designs have an enormous need for better ways to find errors early and en masse. Smarter techniques to isolate errors and apply incremental fixes are also becoming a necessity.
If you are looking to get a quick first pass of the design through the complete flow so that you can get something to work with on the board, gaining EARLY feedback and insight into design specification and setup errors is critical. You may wish to validate functionality by defining specific clear-cut boundaries or points in the design that you want to preserve or probe, or you may want to relate the part of the circuit that is behaving badly back to its RTL to resolve the issue there. You may need some assistance in verifying design setup to catch pilot errors, such as out of date or missing files or incomplete constraints, before you waste hours in synthesis and place and route (P&R). There are several techniques at your disposal to accomplish these tasks, which will be covered in this paper. These techniques include:
- Run synthesis in continue-on-error mode to complete those parts of the design that are error-free and get a report containing most synthesis errors in a single synthesis run
- Run synthesis in fast mode and apply multiprocessing to speed up the runtime while you pipe-clean the design RTL and tune constraints
- Run constraints setup checks prior to synthesis
- Analyze the Gated Clock and Generated Clock Conversion Report early — to ensure constraints