ARC Processor Summit Proceedings
Using Design Time Analysis to Test Security Countermeasures Implemented in ARC SEM Processors
Products in markets including automotive, IoT and payment need high levels of security. One of the main challenges in creating secure systems is to keep encryption keys secure and difficult to derive by an adversary. Side-channels attacks, such as power consumption analysis on data dependent computations, are a known attack to gain access to these encryption keys. Currently testing of side-channel resistant designs requires testing to be performed on the actual silicon. This presentation describes a new tool and methodology using Synopsys' simulators with Riscure's side channel analysis tool to test side-channel countermeasures' effectiveness on an ARC SEM processor prior to implementing them in silicon. The use of this tool will result in fewer tape-outs, lower cost, and shorter time to market.
Jasper van Woudenberg, CTO, Riscure North America
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