ARC Processor Summit Proceedings
Accelerating Group Theoretic Cryptography with ARC APEX Instructions
This presentation will describe how a mathematically efficient cryptographic operation is significantly sped up using the ARC Processor EXtension (APEX) technology. We will give a brief overview of the underlying math operations and how they are implemented in software only. Then we will outline our approach at offloading the most compute-intensive operations onto hardware together with the design process we followed using Synopsys ARChitect, MetaWare, and Intel Quartus Prime. Attendees will see a comparison of the resulting performance metrics with APEX versus an assembly language-only implementation.
The design example will use a fast, small-footprint, and low energy digital signature algorithm that has immediate applicability for a wide range of IoT solutions and is ideally suited for applications where an ARC processor may need to securely communicate with an 8- or 16-bit device. Attendees will learn how to incorporate this and other security methods into their own ARC-based designs.
Drake Smith, Vice President of Development, SecureRF
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