Code efficiency and performance are critical requirements for modern digital signal processing systems. This session will present some key techniques and processor architecture features that can be used to accelerate typical digital signal processing algorithms. DSP examples and optimization strategies will be presented for the DesignWare ARC EM9D and EM11D Processors. ARC Processor EXtension (APEX) technology can accelerate such algorithms, significantly reducing memory footprint. The performance benefits obtained by using APEX can be further leveraged using the XY memory architecture on ARC EM9D and EM11D Processors.
Abhishek Bit, CAE, Synopsys