As chips grow larger, it becomes harder for simulation and analysis solutions to handle the full chip. After all, nanometer designs contain billions of devices. (Ironically, ESD protection circuits themselves could be overdesigned, leading to large die sizes.) With larger chips, transient effects cause more failures. Inductance, capacitance, snapback devices, and larger packages all affect the behavior and need to be modeled to correctly simulate the design. Today’s static ESD checkers are a valuable part of the reliability analysis equation; however, they don’t account for these effects. Reporting of false violations can happen, costing designers time by debugging problems that don’t exist. For example, while decoupling caps improve reliability, they can cause false positives in static tools. To be fair, foundries have done some very clever things to enable some manner of charged-device model (CDM) checking with static checkers. But the industry needs something more comprehensive.
Exhaustive analysis of everything is critical to pinpoint every possible ESD problem, for both HBM (human body model) and CDM events. HBM is the discharge when an individual touches the device. A CDM event happens when a charged device contacts a grounded object. Regarding HBM, the package is sometimes used to reduce the resistive path, while in CDM, the package increases the charge distribution area. Both scenarios require inclusion of the package for correct simulation.
The time that it takes to attempt an exhaustive analysis of a chip also explodes as chip sizes grow. Imagine the challenges with today’s multi-die systems, given all their layers of interdependencies! This is where distributed analysis—taking advantage of parallel processing by distributing the run over multiple CPUs—provides an advantage in turnaround time and coverage.