SystemVerilog Verification using VMM 1.2


In this hands-on workshop, you will learn how to develop a VMM 1.2 implicitly-phased SystemVerilog test environment structure which can implement a number of different test cases with minimal modification. Within this VMM 1.2 environment structure, you will develop replaceable factory components and coverage callbacks, implement scoreboards, manage data communication via TLM 2.0, and describe testing scenarios via mutli-stream generators. Once the VMM 1.2 environment has been created, you will learn how to easily add extensions for more test cases.

After completing the course, you should have developed the skills to write a coverage-driven random stimulus based VMM 1.2 testbench that is robust, re-useable, and scalable.


At the end of this workshop the student should be able to:

  • Develop an VMM 1.2 implicitly-phased environment class in SystemVerilog
  • Implement and manage message loggers for printing to a terminal or file
  • Build and manage transactions
  • Build and manage transactors
  • Build and manage scoreboards
  • Implement communication between transactors using channels and TLM 2.0
  • Implement transaction factories and tests
  • Implement and manage multi-stream scenarios

Audience Profile

Design or Verification engineers who develop SystemVerilog testbenches using VMM 1.2 base classes


To benefit the most from the material presented in this workshop, students should have taken the SystemVerilog Testbench workshop

Course Outline

Day 1

  • SystemVerilog Class Inheritance Review
  • VMM 1.2 Implicitly-Phased Environment
  • VMM 1.2 Infrastructure
  • Modeling Transactions
  • Modeling Transactors

Day 2

  • Managing Communications
  • Modeling Scenario Generators
  • Implementing Scoreboarding
  • Implementing Tests
  • Debug and Optimization Recommendations

Synopsys Tools Used

  • VCS 2010.06