SystemVerilog Verification using VMM 1.1


In this hands-on workshop, you will learn how to develop a VMM 1.1 explicitly-phased SystemVerilog test environment structure which can implement a number of different test cases with minimal modification. Within this VMM 1.1 environment structure, you will develop stimulus factories, check and coverage callbacks, message loggers, transactor managers, and data flow managers. Once the VMM 1.1 environment has been created, you will learn how to easily add extensions for more test cases.

After completing the course, you should have developed the skills to write a coverage-driven random-stimulus-based VMM 1.1 testbench that is robust, re-useable, and scaleable.


At the end of this workshop the student should be able to:

  • Develop an VMM 1.1 explicitly-phased environment class in SystemVerilog
  • Implement and manage message loggers for printing to a terminal or file
  • Build a random stimulus generation factory
  • Build and manage stimulus transaction channels
  • Build and manage stimulus transactors
  • Implement checkers using VMM callback methods
  • Implement functional coverage using VMM callback methods

Audience Profile

Design or Verification engineers who develop SystemVerilog testbenches using VMM 1.1 base classes


To benefit the most from the material presented in this workshop, students should have taken the SystemVerilog Testbench workshop

Course Outline

Day 1

  • SystemVerilog Class Inheritance Review
  • VMM 1.1 Explicitly-Phased Environment
  • Message Service
  • Data model
  • Stimulus Generator/Factory

Day 2

  • Check & Coverage
  • Transactor Implementation
  • Data Flow Control
  • Scenario Generator
  • Recommendations

Synopsys Tools Used

  • VCS 2010.06