Low Power Flow HLD (Front End)


In this workshop, you will perform high-level design steps necessary to synthesize, analyze, and verify a multi-voltage design with shutdown requirements using the IEEE 1801 UPF-based Synopsys Eclypse Low-Power Flow. You will:

  • Identify the library requirements to implement a MV low-power design
  • Create, modify, interpret, and apply power-intent (UPF) files
  • Correctly specify PVT requirements for MV low-power optimizations
  • Perform low-power RTL synthesis using top-down and hierarchical UPF methodologies
  • Generate a gate level design that is MV-clean
  • Insert power-domain aware scan chains
  • Check for logic equivalence of RTL and gate-level designs
  • Conduct static timing analysis on the pre-layout design
  • Analyze average and peak power consumptions
  • Verify the results of running MV rule checks on the gate-level design


At the end of this workshop, using the Front-End Synopsys Eclypse Low-Power Flow, you should be able to perform the following high-level design objectives:

  • Create, interpret, and apply UPF files that capture the stated power intent requirements
  • Synthesize designs for the power intent and power-optimization requirements using both top-down and hierarchical UPF methodologies
  • Describe the effect of performing a supply-net-aware always-on synthesis
  • Insert scan chains taking into account the existing power domains while minimizing switching activity
  • Ensure that the gate-level design is MV clean
  • Ensure equivalence checking of logic functionality between RTL and gate- level using the design and UPF files
  • Perform static timing analysis
  • Generate peak and average power analysis reports/waveforms
  • Analyze gate-level design for MV rule violations
  • Write out all needed files for physical implementation

Audience Profile

Logic design and/or verification engineers who have a need to implement, analyze, and verify designs requiring the lowest possible power consumption using the Synopsys Front-End Eclypse Low Power Flow. CAD Engineers and Managers responsible for Low Power flow will also find this workshop beneficial.


To benefit the most from the material presented in this workshop, students need:

  • A basic working knowledge of Synopsys Design Compiler and PrimeTime tools. Working knowledge of the other Synopsys tools used (list at the end of course description) in the workshop is desirable, but not required, to complete this workshop
  • An awareness of the basics of low-power design techniques. This workshop teaches how to implement these techniques

Course Outline

Day 1

  • Introduction to Low Power Solution
  • Specifying Power Intent: UPF (Lab)
  • RTL Synthesis (Lab)
  • Hierarchical UPF Flow and DFT (Lab)

Day 2

  • Lab-4: Hierarchical UPF Flow and DFT (Lab Contd.)
  • Logic Equivalence Checking (Lab)
  • Static Timing and Power Analysis (Lab)
  • Multi Voltage Rule Checking (Lab)

Synopsys Tools Used

  • Design Compiler - Topographical 2010.03-SP4
  • Design Vision 2010.03-SP4
  • DFT Compiler (with DFTMAX enabled) 2010.03-SP4
  • Power Compiler 2010.03-SP4
  • Formality 2010.03-SP4
  • PrimeTime 2010.06-SP2
  • PrimeTime-PX 2010.06-SP2
  • MVTOOLS (MVRC) 2010.06-3