In this workshop, you learn how to explore the clock tree structure through various reporting commands and how to use the CTS GUI to analyze and verify settings. The workshop goes in-depth into clock tree synthesis methodology and flows for typical 90nm and 65nm designs. You also learn how to use the log to understand the tool messages that are critical to analyzing and debugging CTS results. Reducing clock tree power and avoiding hot spots by careful clock buffer placement is covered. Finally, the basics of MCMM processing of clock trees is considered.
The workshop is accompanied by comprehensive hands-on labs, which provide an opportunity to apply key concepts covered during the lectures.
At the end of this workshop the student should be able to:
- Analyze the clock tree structure prior to running CTS
- Check for valid clock definitions
- Use the clock options correctly
- Identify good vs. bad buffers/inverters for CTS
- Specify different buffers/inverters for specific optimizations within CTS
- Use Non-Default Routing rules (NDR) appropriately
- Describe how to perform clock shielding, how to run low power CTS Flow and use the IC Compiler CTS flows
- Perform clock tree synthesis in debug mode to obtain additional tool messages
- Debug QoR problems
- Optimize clock power before CTS and combat thermal hot-spots by controlling clock cell spacing
- Use the interactive CTS browser to analyze and debug clock structures before and after synthesis
- Use MultiCorner MultiMode technology with the synthesis of the clock trees
ASIC, back-end, or layout designers with experience in standard cell-based automatic Place and Route using IC Compiler.
To benefit the most from the material presented in this workshop, you should:
Have taken IC Compiler 1 workshop.
Possess equivalent knowledge with IC Compiler:
- Script writing using Tcl
- Reading and linking a design
- Using IC Compiler's graphical user interface (GUI)
- Generating and interpreting timing reports using report_timing and report_constraint commands
- Pre-CTS Check and Setup
- Building Clock Trees
- Debugging and Refining Clock Trees
Synopsys Tools Used