Conference at a Glance

SNUG Taiwan | September 15-16, 2015

Tuesday, September 15, 2015
Wednesday, September 16, 2015

Tuesday, September 15, 2015

 Time

Description 

8:30-9:10 Registration
9:10-10:00 Welcome and Synopsys Keynote
At the Heart of Electronics, Design Makes Everything Different
Dr. Antun Domic, Executive Vice President and General Manager, Design Group - Synopsys

10:00-10:40 Industry Keynote
Everyday Genius - How Design Makes Technology Better
Andrew Chang, Corporate Senior Vice President - MediaTek, Inc.
10:40-11:00 Break
11:00-11:40 Industry Keynote
I.O.T. Foundry with Green DNA
Bill Chuang, Marketing Director - United Microelectronics Corporation
11:40-12:00 SNUG Taiwan Technical Committee Presentation
Denny Liu, Special Assistant - MediaTek, Chairperson - SNUG Taiwan 2015 Technical Committee
12:00-1:30 Panel Luncheon - An Ecosystem Panel Perspective on Successfully Designing with FinFET
1:30-3:30

TA1 - Implementation I

TA1.1 UPF Partitioning Challenges in DVFS Era

TA1.2 IC Compiler Multisource CTS - Practical Experience Sharing


TA1.3 An ICC II Approach for Timing Closure in Advanced Nodes


TA1.4 IC Compiler's Latest Release (2014.09) Delivers Significant Performance Power Area Improvements and Faster Closure on Emerging and Established Nodes

TA2 - Implementation II

TA2.1 Design Compiler Graphical For High Performance Core Design

TA2.2 Synthesis Strategies for DVFS Designs

TA3 - Verification Continuum

TA3.1USB Test Suite - The Window to Successful Verification

TA3.2 Divide and Conquer of MIPI CSI2 MAC and PHY Verification

TA3.3 Utilizing VIP Testsuites

TA4 - Integrated AMS Solution

TA4.1 TSMC FinFET reference flow using Synopsys Custom Designer and Laker

TA4.2 How Custom Designer Can Improve Your Circuit Design and Simulation Productivity

TA4.3 Experience Sharing of FineSim Tool Usage in Flash Design

TA5 - Hybrid Prototyping

Multi-FPGA Prototyping of 1.5 Billion ASIC Gates

TA5.2 Earliest SW/HW Co-Development for Complex SoCs Using ProtoCompiler Enabled FPGA Prototyping Platforms

TA5.3 X-Ray Vision - High Visibility Multi-FPGA Debug for FPGA-Based Prototypes

TA6 - Software Quality

TA6.1 Introduction to Software Quality and Security in the Emerging Internet of Things

TA6.2 Introduction to Vulnerability Management

3:30-4:00 Break
4:00-6:00

TB1 - Implementation I

TB1.1 Quick Migrate to IC Compiler II

TB1.2 Differentiated ICC II Technologies for Handling Large SoC

TB1.3 Boost Productivity Using ICC II - A Multimedia Block Case Study

TB1.4 ARM Cortex-A53 Multi-Core Network Computing Reference Implementation on Samsung 14LPP FinFET Process

TB2 - Implementation II

TB2.1 PrimeTime Timing and Power ECO Practical Experiment Result

TB2.2 Large Scale Design STA - Hierarchical or Flat, Distributed or Single Machine - Which Way to Go for Timing Signoff?

TB2.3 Design Compiler and Formality 2015.06 Update

TB3 - Verification Continuum

TB3.1 UPF Modeling of Retention Register

TB3.2 Universal Low Power Verification of Multi-Apps SoC

TB3.3 Overview of Synopsys Memory VIP

TB4 - Integrated AMS Solution

TB4.1 SiliconSmart Performance and FR Enhancement on Standard Cell

TB4.2 Standard Cell and Mixed-Signal IP Characterization Using SiliconSmart

TB4.3 Timing Analysis of Self-Timed SRAM Designs by Using NanoTime for Memory with Dynamic Clock Simulation Feature

TB4.4 Innovations in Fast and Accurate Transistor-level Simulation Using HSPICE, FineSim SPICE, and WaveView for Post Processing

TB5 - Hybrid Prototyping

TB5.1 Prototypes on High Speed Rails - When Schedule is the Priority

TB5.2 Power-Aware Architecture Design for Multicore SoCs

TB5.3 Fast IP Software Development & Integration with Virtual & FPGA-Based Prototyping - DesignWare Hybrid IP Prototyping Kits

 


Wednesday, September 16, 2015

 Time

Description 

8:30-9:10 Registration
9:10-10:00 Welcome and Verification Direction Presentation
Synopsys Verification Direction - Rethinking SoC Verification
Ken Nelsen, Vice President, Global Technical Services - Synopsys
10:00-10:20 Best Paper Award
Denny Liu, Special Assistant - MediaTek, Chairperson - SNUG Taiwan 2015 Technical Committee
10:20-10:40 Break
10:40-11:20 Industry Keynote
Flash Memory History and Phison
K.S. Pua, Founder, Chairman, and CEO - PHISON Electronics Corp.
11:20-12:00 Industry Keynote
Five Must-Knows for the Semiconductor Industry in the Internet of Things
Jui-Lin Yang, Deputy Program Director – Industrial Economics & Knowledge Center, Industrial Technology Research Institute
12:00-1:30 Lunch
1:30-3:00

WA1 - Implementation I

WA1.1 High-Performance, Energy Efficient Implementation of the ARM Cortex-A72 Processor Core in 16-nanometer FinFET Plus (16FF+) Process Technology Using Synopsys Galaxy Design Platform

WA1.2 IC Complier II - Accelerating Products to Market

WA2 - Implementation II

WA2.1 High Quality Transition Test with Synchronous OCC for Scan-Based Design

WA2.2 Test Quality Improvement Using Advanced Fault Models

WA2.4 Meet Your Test Quality and Cost Goals on Schedule

WA3 - Verification Continuum I

WA3.1 Automated Flow Using Formal Methodology to Reach Hundred Percent Line Coverage

WA3.2 VC-Platform and VC-APPs integration - Multiple Power Domain Fanout Nets

WA3.3 New Methodology for Power Estimation in ASIC Early Stage - Siloti Power Estimation Flow

WA3.4 Accurate and 10x Speedup Power Consumption Analysis at Early Design Stage with Siloti/Verdi3/VC-Apps

WA4 - Integrated AMS Solution

WA4.1 Run Time Improvement by Power Net RC Optimization with Automatic Power Net Identification Feature of CustomSim

WA4.2 TMI Modeling for FinFET IC Simulation

WA4.3 CustomSim Updates for Circuit Simulation

WA5 - IP

WA5.1 Energy Harvesting, Sensors, and SoC's for the IoT Era

WA5.2 IMG GPU Implementation Using SNPS Libraries, Memories, and SMS for 16FF+

3:30-4:00 Break
4:00-6:00

WB1 - Implementation I

WB1.1 IC Complier II Marketing and R&D Update

WB1.2 IC Compiler II Technology Tutorial

WB2 - Implementation II

WB2.1 Accelerating Manufacturing Compliance Using ICV In-Design Flow Within IC Compiler II for Emerging Technology Nodes

WB2.2 Dynamic IR Analysis with RTL-VCD Flow at Earlier Stage

WB2.3 PrimeRail - Using Advanced Rail Analysis in the In-Design IC Compiler Implementation Flow

WB4 - Integrated AMS Solution

WB4.1 Circuit Design and Simulation Implementation in CDSE/SAE

WB4.2 Accelerating Physical Design Flow in Laker with TCL Applications and Third Party Tool Integration

WB4.3 Synopsys Custom Layout Integration Flow Overview

WB5 - IP

WB5.1 Optimize DDR Memory Subsystems for Performance, Power, and Cost

WB6 - Verification Continuum II

WB6.1 Universal and Integrated Platform of Debug and Verification

WB6.2 Best Practices for Linux Driver Development and RTL Behavior Analysis in PCIE Hybrid Emulation

4:30-7:00 Sponsor Expo