Conference at a Glance

SNUG Silicon Valley | March 23-25, 2015

Monday, March 23, 2015
Tuesday, March 24, 2015
Wednesday, March 25, 2015

Monday, March 23, 2015



7:30-8:45 Registration and Breakfast
9:00-10:30 Welcome and Keynote: Silicon to Software - Scale Complexity, Systemic Complexity, and Software Complexity
10:30-11:00 Break

Implementation 1

Implementation 2

Implementation 3

Verification 1

Verification 2


Circuit Simulation


Signoff and Characterization

IP Summit


MA-01 ICC II Technology

IC Compiler II Technology Tutorial

MA-02 Frontend Implementation

An Optimal Approach for Datapath Implementation and Verification Methodology

Who Put Assertions In My RTL Code? And Why? How RTL Design Engineers Can Benefit from the Use of SystemVerilog Assertions

MA-03 Low-Power Implementation

UPF-Based Static Low-Power Verification in Complex Power Structure SoC Design Using VCLP

Power Intent (UPF) Based Synthesis Flow for Multimillion Gate Complex SoCs

MA-04 Verification Direction

Synopsys Verification Direction


MA-07 Circuit Simulation

HSPICE MOSRA Aging Simulation Considering Self-Heating Effect

Technical Committee Award: 2nd Place - Best Paper 2nd place, Technical Committee Award Winner

Technology Inflection Points - Planar to FinFET to Nanowire

MA-08 Prototyping

Tales of Rapid Prototyping Heroes - Finding Multi-FPGA Partition Solutions Fast

MA-09 Signoff for Advanced Node SoCs

Large Scale Design STA - Hierarchical or Flat, Distributed or Single Machine: Which Way to Go for Timing Signoff?

What Every Designer Needs to Know About 16/14nm Library and STA Requirements

MA-10 Optimizing DDR Memory Subsystems

Optimize DDR Memory Subsystems for Performance, Power, and Cost

12:30-2:00 Networking Lunch
12:30-2:00 MA-11 IP Lunch and Learn - Energy Harvesting, Sensors, and SoCs for the IoT Era
12:30-2:00 MA-12 Implementation Lunch and Learn - IC Compiler II - Accelerating Products to Market with the Power of 10X

MB-01 Frontend Implementation

Achieving Optimal Quality of Results Faster with Design Compiler

MB-02 Physical Implementation

A Hybrid IC Compiler II-Based Flow for Rapid Design Closure

The Rubber Jigsaw Puzzle - Floorplanning for Network-on-Chip

MB-03 Implementation Flows - IP for Memristor Development and Wireless Sensor Node Minimum Energy Design

Microcontroller Hard IP for Memristor Development ICs in 30 Days

Minimum Energy Design for Sub-threshold Wireless Sensor Nodes

MB-04 VCS Save/Restore and Microprocessor Emulation

Improving Verification Productivity of Embedded C Tests Using the VCS Save/Restore Feature

Validating VISC Microprocessor in Emulation

MB-05 VCS Performance and Golden UPF

VCS Optimization Techniques for Multi-Chip Simulations

Challenges and Benefits of Deploying a Master UPF Flow

MB-06 Software Testing with Coverity Part 1 of 2

Best Practices in Software Testing using Coverity Tools

MB-07 Circuit Simulation

Accelerating Analog IP Characterization & Verification by FlexIP Using Custom Design, HSPICE, and Custom WaveView

How the Custom Designer Simulation and Analysis Environment (SAE) Can Improve Your Circuit Simulation Productivity

MB-08 Prototyping

ATOM Mobile SoC Performance and Power Architecture Exploration

Build and Integrate Your Own Custom IO Interfaces for Your HAPS-Based SOC Prototype

MB-09 Signoff - POCV/LVF Variation Modeling

Latest Advancements for Handling Local Variation Effects in Timing Analysis

Improving Design to Sign-off Correlation with Parametric On-chip Variation

MB-10 Conexant ASIP Implementation and IP Prototyping Kits

Design of Application Specific Processor for Far-field Voice Processing

Configure, Integrate, and Prototype IP in Minutes

3:30-3:45 Break

MC-01 FinFET Panel

Successfully Designing with FinFET

MC-02 Physical Implementation

Unlock IC Compiler II's "Power of 10X" Using Lynx Design System

MC-03 Test

SoC Test, Repair, and Diagnostics with STAR Memory System and STAR Hierarchical System

MC-04 Verification Compiler Overview

Verification Compiler Overview

MC-05 Multi-Processor HW/SW Debug and Reusable Testbenches

Multi Processor SoC Debug with Synopsys Hardware Software Debug Tool

Compile-time Parameter Distribution for Highly Reusable Testbenches

MC-06 Software Testing with Coverity Part 2 of 2

Best Practices in Software Testing with Coverity - Continued

MC-07 Circuit Simulators Update

Innovations in Fast and Accurate Transistor-level Simulation Using HSPICE, FineSim SPICE, and WaveView for Post Processing

CustomSim Updates for Circuit Simulation

MC-08 Prototyping

X-Ray Vision - High Visibility Multi-FPGA Debug for FPGA-Based Prototypes

MC-09 Static Timing Analysis Flow Topics

Sign-off Based Leakage Power Recovery in PrimeTime

Minimum Set of PrimeTime Timing Signoff Corners

MC-10 Hardening GPUs with Memories and Libraries

Hardening Imagination's 16FF+ PowerVR Series7 GPU for Performance & Power with DesignWare HPC Design Kit

4:00-8:00 Designer Community Expo

Tuesday, March 24, 2015



8:00-9:00 Registration and Breakfast
9:00-10:00 Keynote Address - IoT - The Internet of Completely Different Things
Dr. Dipesh Patel - EVP Technical Operations, ARM
10:00-10:30 Break

Implementation 1

Implementation 2

Implementation 3

Verification 1

Verification 2



Signoff and Characterization 1

Signoff and Characterization 2

IP Summit


TA-01 In-Design Physical Implementation

Customer Experiences with IC Compiler In-Design for Metal Fill, Pattern Matching, and Automatic Double Patterning Fixing on Advanced Nodes

TA-02 Physical Implementation

CTS Challenges of Complex Clock Structure Design

Area-centric Reference Implementation Flow for ARM Mali Cost-Efficient GPUs

TA-03 Test

Meet Your Test Quality and Cost Goals on Schedule

TA-04 VC Apps Developer Forum

VC Apps Developer Forum - Enhancing Debug Productivity

TA-05 ZeBu Tutorial

Leveraging ZeBu for Simulation Acceleration and Early SW Validation*

TA-06 Introduction to Software Quality and Security

Introduction to Software Quality and Security in the Emerging Internet of Things

TA-07 Prototyping

Speed - Reveal Your Prototype's Performance Superpower - Synopsys HAPS High-Speed Time Domain Multiplexing (HSTDM)

TA-08 Statistical Characterization and Library Qualification

Tightening Hold Margins Using Monte Carlo Simulation

Standard Cell Qualification with SiliconSmart

TA-10 Embedding Vision into SoCs

Embedding Vision into Your SoCs

12:00-1:30 Networking Lunch
12:00-1:30 TA-11 Verification Lunch and Learn - Addressing SoC Complexity Across the Verification Continuum
12:00-1:30 TA-12 Design Compiler Lunch and Learn - Accelerating Innovation with Design Compiler

Implementation 1

Implementation 2

Implementation 3

Verification 1

Verification 2

FPGA Design


Signoff and Characterization 1

Signoff and Characterization 2

IP Summit


TB-01 High-Performance Core Implementation

Renesas Shares Highlights from Their Successful Implementation of an ARM Cortex-A57 MPCore Processor in 16-nm FinFET Plus Process Technology Using Synopsys Galaxy Design Platform

High-Performance, Energy Efficient Implementation of the ARM Cortex-A72 Processor Core in 16-nanometer FinFET Plus (16FF+) Process Technology Using Synopsys Galaxy Design Platform

TB-02 Multi-bit Implementation and Formal Verification

Formality and Formality Ultra Update

Verilog-to-Verilog Equivalence Checking Using ESP-CV

Reducing Clock Dynamic Power Using Multi-bit Register in High Performance Designs Using DCG/ICC

TB-03 Test

Volume Physical Diagnostics for Faster Yield Ramp

Compression Chain Diagnosis

Achieving High Compression Ratios with Cell-Constrained Designs Using DFTMAX Ultra

TB-04 Assertion Optimization, Full-chip Simulation, and AMS Behavioral Modeling

A Method to Dynamically Disable/Enable SystemVerilog Assertions

Full-Chip Simulations, Keys to Success

Technical Committee Award: 3rd Place - Best Paper 3rd place, Technical Committee Award Winner

Flow for Equivalence Checking and Accuracy of Real Number Based Analog Models

TB-05 GPU Emulation, Constraint Debug and Analysis, and UVM

Enabling Greater Reliability, Scalability, and Flexibility of GPU Emulation with a Hybrid Virtual Machine Based Approach

Using Verdi to Understand Constraint Gotchas, Debug Solver Failures, and Optimize Your Constraints

Technical Committee Award: 1st Place - Best Paper 1st place, Technical Committee Award Winner

RESSL UVM Sequences to the Mat

TB-06 FPGA Synthesis

ASIC to FPGA-based Prototype Conversion

TB-07 Prototyping

IP Power Modelling for Energy Aware Architecture Design

Turning Your Power Spreadsheet into a Virtual Prototype for Energy-Aware Architecture Design

TB-08 Memory and POCV Aware Macro Sign-off and Characterization

SRAM Analysis and Characterization Using NanoTime for Memories

Transistor Level Parametric On-Chip Variation (POCV) Setup and Analysis

TB-09 StarRC Advances in Performance and Process Technology - User Experiences

Fast ECO Extraction and Other Techniques for Optimizing Timing Closure TAT

Fast, Accurate Extraction of High-Frequency Design using StarRC - AMD Update

Achieving Significant Productivity Improvement with StarRC Simultaneous Multi-Corner Solution - APM Experience

Achieving Highest Accuracy FinFET Extraction with StarRC "QuickCap Inside" Solution

TB-10 SerDes PHY Selection and Interface IP Subsystems

Choosing the Right SerDes PHY IP to Differentiate Your SoC

Reduce the Effort and Cost of Integrating Interface IP Subsystems into SoCs

3:30-3:45 Break

TC-01 ICC II R&D Panel

Enabling the Power of 10X on Advanced Designs Using IC Compiler II

TC-02 Advanced Physical Implementation

Challenges and Solutions for 14nm Design Flows

TC-03 Test Panel

Is It Possible to Lower Test Costs (Even More)?

TC-04 VC Formal and VC CDC

New Static Technologies - VC Formal Platform

New Static Technologies - Clock Domain Crossing

TC-05 Verdi Advanced Debug

Verdi Debug Platform (Planning, Coverage, HW/SW, AMS)

TC-07 Prototyping

Successful Complex GPU IP Implementation on Synopsys HAPS Platforms Using ProtoCompiler

TC-09 Signoff Physical Verification

Current Density and Balanced Layout Checking Utilizing Programmable Extended ERC Checking with IC Validator

TC-10 IP for Energy-Efficient IoT Designs

IP That Will Drive Energy-Efficient IoT Designs

5:00-6:30 SNUG Pub

Wednesday, March 25, 2015



8:00-9:00 Registration and Breakfast

Implementation 1

Implementation 2

Implementation 3

Verification 1

Verification 2

FPGA Design

Compute Infrastructure



Getting Productive in the ICCII GUI

WA-02 Custom Physical Implementation

Custom Design with FinFETs, Best Practices Designing Mixed-Signal IP

Handling Electromigration for Custom Design with FinFET Devices Using Custom Designer

WA-03 Rail Implementation and Analysis

PrimeRail - Using Advanced Rail Analysis in the In-Design IC Compiler Implementation Flow

WA-04 VIP Test Suite

Utilizing VIP Test Suites


Navigating Your Way Toward UVM Version 1.2 - What's New About UVM v1.2

UVM Message Display Commands Capabilities, Proper Usage and Guidelines

WA-06 FPGA Synthesis

Best Practices for Boosting Timing Performance Results in Your FPGA

WA-07 Optimizing Storage Infrastructure

Accelerating Library Characterization Through Infrastructure Optimization

An Apparatus for Quantifying and Replaying Consolidated EDA Workload

10:30-10:45 Break

WB-01 ICC Update

IC Compiler's Latest Release (2014.09) Delivers Significant Performance Power Area Improvements and Faster Closure on Emerging and Established Nodes

WB-02 Custom Implementation

How to Make the Most Out of Your oaScripts by Using oaxPop Example

WB-03 Test - Scan Diagnostics

Six Ways that Scan Diagnostics Drives Silicon Learning

WB-04 VCS 2014.12 Update

VCS-MX 2014.12 Update


Verifying Mixed-Signal SoCs

WB-06 FPGA Synthesis

How to Bring Up and Complete Your FPGA Design with Faster and Fewer Iterations

WB-07 High-Performance Computing for Silicon Design

High-Performance Computing for Silicon Design

12:15-1:45 Networking Lunch
12:15-1:45 WB-08 Lynx Lunch and Learn - Design Exploration to Accelerate PPA Closure of a Mobile Computing ARM Cortex-A53 Targeting Samsung Foundry 28LPP and 14LPP FinFET Technology with Lynx Design System

1:45-2:15 Awards and 25th Anniversary Celebration

*Notice to ZeBu Users
ZeBu SW version 2014.12 should only be used on ZeBu systems which are located and accessed exclusively from outside the U.S. Synopsys will not support version 2014.12 on systems located in or accessed from the U.S.

ZeBu SW versions 2014.09 and earlier should only be used on ZeBu systems sold in the U.S. prior to October 10, 2014, or on ZeBu systems which are located and accessed exclusively from outside the U.S. Synopsys will not support version 2014.09 and earlier on systems sold after October 10, 2014 and accessed from the U.S.