| Time |
Description |
| 8:00-8:50 |
Registration - Grand Ballroom 2 & 3, Level 1 |
| 8:50-9:00 |
WELCOME - SNUG Singapore Introduction |
| 9:00-9:45 |
Keynote Address: - Grand Ballroom 2 & 3,
Level 1
Enabling Infinite Possibilities in Cloud Era
Mr. Ku Chung-Chiang, General Manager
MediaTek Singapore Pte Ltd |
| 9:45-9:50 |
SNUG Technical Committee Introduction |
| 9:50-10:15 |
Tea Break - Grand Ballroom Foyer, Level 1 |
| |
Frontend Design - Track I
Grand Ballroom 3, Level 1
|
Frontend Design - Track II
Grand Ballroom 2, Level 1
|
Backend Design Track
Grand Ballroom 1, Level 1
|
Verification Track
The Boardroom, Level 1
|
| 10:15-10:45 |
User Paper 1: A Comprehensive Methodology for IDDQ Signoff
|
User Paper 1: Optimum Leakage Recovery using Synopsys PrimeTime ECO Leakage Recovery Flow
|
User Paper 1: CMP Driven Lithography Design Optimization Using Synopsys ICC / ICV
|
Tutorial: VCS 2014.03 Release Highlights
|
| 10:45-11:15 |
User Paper 2: Minimizing Modifications Required for UMR Capim Addition
|
User Paper 2: Novel Retention Synchronizer Flip-Flop Translation Method in Synthesis Flow
|
User Paper 2: An Advanced Approach to Optimize Hierarchical Pin Assignment
|
Tutorial: The "X" Factor: Address it in RTL Simulations
|
| 11:15-11:45 |
User Paper 3: Evaluation of ARC Processors Using Synopsys Tools
|
User Paper 3: Innovative Clock-Domain Aware DFT Concept Based on Tetramax to Improve Timing Closure of Most Complex SoC Designs
|
User Paper 3: More than Waiver - Automating Regession of Design Rule Deck
|
Tutorial: Going Beyond the Waveform: Advance Debug Techniques in Verdi
|
| 11:45-12:15 |
User Paper 4: Using Synopsys Asynchronous OCC IP to Target Cross Clock Domain Faults
|
User Paper 4: Single Static Timing Analysis Run for Multi Mode Peripherals in SoC Design
|
User Paper 4: Faster Timing Closure with Concurrent Clock and Data Optimization
|
| 12:15-1:00 |
Lunch - Sky Ballroom Level 1 |
| 1:00-2:00 |
Technology Keynote: - Grand Ballroom 2 & 3,
Level 1
Advanced EDA at Every Node
Mr. Don Chan,
Vice President of Corporate Applications Engineering, Design Group, Synopsys Inc |
| 2:00-3:00 |
Synopsys Verification Vision - Grand Ballroom Foyer, Level 1
Mr. Ken Nelsen,
Vice President, Applications Consulting, Global Technical Services Synopsys |
| 3:00-3:20 |
Tea Break - Grand Ballroom Foyer, Level 1 |
| |
Frontend Design - Track I
Grand Ballroom 3, Level 1
|
Frontend Design - Track II
Grand Ballroom 2, Level 1
|
Backend Design Track
Grand Ballroom 1, Level 1
|
AMS Design Track
The Boardroom, Level 1
|
| 3:20-3:50 |
User Paper 5: Hybrid and Shared Codec: A Case Study
|
User Paper 5: SCAN Through SMS Memories
|
User Paper 5: A Novel Strategy for Design Implemention of A High Speed Low Power SOC with 5 Million Instance Count
|
Tutorial: Advance Layout Techniques in 16/14nm Designs |
| 3:50-4:20 |
Tutorial: Design Compiler 2013.12 Release Highlights
(3:50 pm - 4:35 pm)
|
Tutorial: PrimeTime ECO - Now Physically Aware
(3:50 pm - 4:35 pm)
|
User Paper 6: Continuous RX Standard Cell Placement Support in ICC for GLOBALFOUNDRIES 20nm & Below Technologies
|
| 4:20-5:20 |
Tutorial: DFTMAX Ultra
(4:35 pm - 5:20 pm) |
Tutorial: VC LP: Next-Generation Low-Power Static Verification
(4:35 pm - 5:20 pm) |
Tutorial: IC Compiler II and the Power of 10x: A Product Walk-Through |
Tutorial: Transistor Level Reliability Analysis in Advance Node Geometry Design |
| 5:20-5:45 |
Best Paper Awards & Lucky Draw! - Sky Ballroom,
Level 1 |
