Conference at a Glance

SNUG Canada | October, 8, 2014

Wednesday, October 8, 2014



8:00-9:00 Registration and Breakfast
9:00-10:30 Welcome & Introduction: Costas Conistis, Synopsys & Technical Chair Paul Lungu, Ciena

Keynote Address: Addressing Today's Increasing Design Complexity Through Innovation and Collaboration
Chi-Foon Chan, President and co-CEO - Synopsys
10:30-10:45 Break


Implementation 1

Implementation 2

Analog Mixed Signal


A1-Vision Session - Verification

Verification Compiler; Rethinking Verification

A2-User Session - VC Low Power and Test

VC LP User Experience

Slacking Off on DFT: Slack-Based Test of Multi-Cycle Paths with a Physical View of Results

2nd Place - Best Presentation 2nd Place - Best Presentation

A3-User & Tutorial Session - PrimeTime ECO and Physically Aware ECO

Last Mile Solutions for High Speed Designs in Advanced 16nm Nodes

PrimeTime ECO - Now Physically Aware

A4-Tutorial Session - Custom Designer SAE

SAE: A Flexible, Easy to Use Simulation Cockpit For Analog Designers

Synopsys Custom Design Platform Tutorial

12:15-1:15 Networking Lunch


Implementation 1

Implementation 2

System Emulation and
Hardware Verification


B1-User Session - Advance Verification Session

What is the Quality of Your DV Environment?

Using VCS Save/Restore to Optimize License Usage

Functional Design Bugs Detected with Low Power Verification

B2-Tutorial & User Session - ICC II Walk-Through and Multicycle Paths

IC Compiler II and the Power of 10x - A Product Walk-Through

RTL Designers Can Have a Cake (Low Power) and Eat It Too (Relaxed Path Timing)

Technical Committee Best Paper Award Technical Committee Award Winner - Best Paper

B2.3 Effective Design using Multi-Cycle Paths with Assertions

B3-Tutorial Session - ICC II Product Walk-Through and FM Ultra

IC Compiler II and the Power of 10x - A Product Walk-Through

Functional ECOs Made Easier with Formality Ultra

B4-User & Tutorial Session - HAPS, Zebu and VDK's

Test IP: Bringing the Tools and Methodology from Pre-Silicon Verification to Post-Silicon Validation

Performance Analysis for the Synopsys DesignWare Universal DDR Memory Controller Using Synopsys Platform Architect MCO

Verification of SoC Designs with ZeBu HW Emulator

3:15-3:30 Break

C1-User Session - Advance Verification Environment

Verification Without DUT

SoIP Verification Using the UVM Register Model

Snakenado - A Modular and Open-Ended Register Solution

C2-Tutorial & User Session - 2014 DC Update and Lynx

Design Compiler 2014.09 Highlights

Enabling Additional Implementation Tasks in Lynx

C3-User Session: Timing DRCs and Clock Generation

Topology-aware Net Splitting for Faster Timing DRC Closure

3rd Place - Best Presentation 3rd Place - Best Presentation

Dynamic Clock Generation with Useful Skew

1st Place - Best Presentation 1st Place - Best Presentation


C4-Tutorial Session - Integrating Siloti and HAPS

Integrating Siloti into Live FPGA Debug

Integrating Synphony's High-Level Models with HAPS Prototyping Systems

4:45-6:00 SNUG Pub and Awards Presentation