Conference at a Glance

SNUG Taiwan | September 10-11, 2013

Tuesday, September 10, 2013
Wednesday, September 11, 2013

Tuesday, September 10, 2013



8:30-9:10 Registration
9:10-10:00 Welcome and Synopsys Keynote
Accelerating Innovation in the Era of Exponentials
Manoj Gandhi, Senior Vice President & General Manager, Verification Group, Synopsys

10:00-10:20 Welcome - SNUG Technical Committee
Wen-Hung Wu, SNUG Taiwan Technical Committee Chairperson

10:20-10:40 Break
10:40-11:20 Customer Keynote
Speed up Everything - Driving Fabless Company Innovation by an EDA Group
Andrew Chang, Corporate Vice President, MediaTek
11:20-12:00 Technology Keynote
Investing the Future - From 2D to 3D
Frank Lee, Director, TSMC
12:00-1:30 Lunch

TA1 - HPC Implementation and Panel

Proving the 20nm Implementation Ecosystem Using an ARM Mali GPU with a Full Galaxy Tool Flow

HPC Panel - Achieving Optimum Results on High-Performance Processor Cores

TA2 - Test/IP

Era of IP

Port Limit Solution - JTAG Base Test Mode Decoder

DFTMAX with Serializer Architecture for I/O Limit

Memory Repair Solution With Synopsys SMS

TA3 - Circuit Simulation

CustomSim Native IR/EM Solution

Experience Sharing on Improving Simulation Time With Power Generator Circuit

Mixed-Signal Design Verification Using Co-simulation With VCS-XA

A Practical Look at Current Analysis in FastSpice

TA4 - Verification

A Reusable Verification Testbench Architecture Supporting C and UVM Mixed Tests Best Paper Award

Does Power State Table Matter in Low Power Verification? Best Paper Award

Macro Power Aware Simulation Dilemma: UPF or DB

VCS for Best Performance

3:30-4:00 Break

TB1 - HPC Implementation

Rectilinear Shape Floorplan and High Density Mali 400 Design with TSMC 28nm HPM process

Power-Centric Timing Optimization Flow for an ARM® Cortex™-A7 Quad Core Processor

Engineering Trade-Offs in the Implementation of a High Performance Dual Core ARM® Cortex™-A15 Processor

TB2 - Static Timing Analysis

IDEA: Innovative AOCV Design Flow with Efficiency and Accuracy

Achieving Timing Closure on Hundred Million Gates SoC Design with ETM & ILM Best Paper Award

Signoff Driven Timing Closure with PrimeTime: Now Includes Leakage Reduction

Using Mode-Merging to Reduce Scenarios Required for Timing Closure and Signoff

TB3 - IP and Ecosystem

UMC Advanced IP - SOC Design

HDMI 2.0 & MHL 2.0: The Future of Multimedia Connectivity

Considerations for Timing Budgets for DDR4 Interfaces

TB4 - VIP/Verification

Migrate from DWVIP to Discovery VIP

HW/SW Verification and Debug with VCS and Verdi3

Achieving Performance Verification of ARM Processor-based SoCs Optimizing and Validating the Performance of Your AMBA® based Interconnect

Wednesday, September 11, 2013



8:30-9:10 Registration
9:10-10:00 Welcome and Synopsys Keynote
Accelerating Innovation in Electronics That Impact Everything, Everyone, Everywhere
Paul Lo, Senior Vice President & General Manager, Analog/Mixed Signal Group, Synopsys

10:00-10:20 Break
10:20-10:40 Best Paper Award
SNUG Taiwan Technical Committee Chair

10:40-11:20 Technology Keynote
Kuo-Cheng Chang, Vice President and Spokesperson, RICHTEK
11:20-12:00 Technology Keynote
The Fate of the Logic Designer and Future Design Challenge
Jiin Lai, Chief Technology Officer, VIA
12:00-1:30 Lunch

WA1 - HPC and Advanced Technology

Implementation Experience Sharing with UMC 28HLP

Preparing for the Next Decade

WA2 - Synthesis

Fast And Reliable PPA (Power/Performance/Area) Exploration by DC Explorer

DC-Explore Experience Sharing


WA3 - System

Experiences on System Integration with the CoStart for VDKs

The Design of Embedded Vision Systems

WA4 - Custom Design Using Laker

TSMC iPDK Update

Advanced-Node Layout Requirements

Laker CDPR (Custom Design Place and Route) on DRAM

LakerBlitz - Chip Level Layout Editor

WA5 - Debugging with Verdi

Create Power Intent and Verify Power Policy by Verdi3

How do you Debug Power Related Issues? - A Methodology for Low Power Debug

Realize Your Own Ideas with Rich APPs Inside Verdi's VIA Toolbox

3:00-3:30 Break

WB1 - Physical Implementation

Time-to-Result Using Lynx on ARM Cortex A9-based SoC Design with UMC40LP

Design with Non-Planar CMOS and Double-Patterning

Routing a Synopsys DDR PHY's Matched Pair Signals Using Galaxy Custom Router and ICC (with Co-Design), Within Lynx

WB3 - Emulation and FPGA-Based Prototyping

Emulator Virtual Platform Design Methodology

Complex SoC Prototyping Using Xilinx Virtex 7 Based HAPS-70 Systems

Quick FPGA Prototype Platform Bring-up and Design Debug

WB4 - Custom Design Using Laker

Laker FPD Application on e-Paper Design

iPDKs: A Thriving PDK Standard

UMC iPDK Program: Development and Validation

Powerful and Comprehensive Devices in Laker

WB5 - Debugging with Verdi

Exploring Protolink: Effective Debugging from Firmware to Hardware

Customer Case Study: Validation of ARM Systems using FPGAs and ProtoLink

Verdi Transaction Based Debugging for SoC Designs

Functional Signoff: A Process for Measuring and Improving Verification Quality to Ensure Bug-Free Designs

5:00-7:00 Sponsor Expo & Lucky Draw, Meeting Room B