Conference at a Glance

SNUG Singapore | August 16, 2013

Friday, August 16, 2013



8:00-8:50 Registration - Olivia Ballroom Level 4
8:50-9:00 Welcome to SNUG Singapore
9:00-9:45 Keynote Address:
An Engineer Experience Moving from a MNC to a Technology Start-Up
Dr. TAN Guan Hong , Programme Director Institute for Infocomm Research, I2R
9:45-9:55 SNUG Technical Committee Introduction
9:55-10:15 Tea Break - Stamford Foyer Level 4

Design Implementation - Track I
Olivia Ballroom Level 4

Design Implementation - Track II
Sophia Ballroom Level 4

Verification & AMS Custom Design
VIP B Ballroom

Tutorial & Breakout Session
Canning Ballroom Level 4


Timing Sign-Off Methodology in 20nm Technology: Process and Design Perspective

An Overview of Quad-Core A7 CPU Implementation

A Realistic Approach To Account LDE Effect In Timing Library Characterization

Tutorial: AMS Designs in Advance Node


Cone Extraction Technique for Incremental Static Timing Analysis

Sign-Off Accuracy Hierarchical Design Interface Timing Budgeting Flow in SoC Design

Automating SoC Based UVM Verification Environments

Tutorial: Accelerate Functional ECO Implementation with Formality Ultra


Design and Implementation of Custom On-Chip Clock Controller

Assistive Split Load Utility for High Fanout Clock Maximum Transition Violations

Analog Mixed-Signal Simulation in VCS

Tutorial: Quick FPGA Prototying Platform Bring-up and Design Debug


Design Explorer - The "Little" Design Compiler That Punches Above its Weight

DFM Driven Scan Failure Analysis Using Synopsys Yield Explorer

Python Based Layout Automation Practice with PyCell Studio

12:15-1:15 Lunch - Canning Ballroom Level 4

Technology Keynote: - Olivia Ballroom Level 4
Advanced Design, Regardless of Process Technology Node
Mr. Don Chan, Vice President, Research and Development, Synopsys Inc.


Better ICC to PrimeTime Correlation with Pseudo AOCV Table

Parallel ECO Work Model

Abstract PCell Schematic


A Novel Approach of FPGA-Based ATPG Scan Compression

Optimum Design Planning with DC-Graphical and ICC-DP

Tutorial: UVM Best Practices

3:15-3:30 Tea Break - Stamford Foyer Level 4

Tutorial: Galaxy-ECO: The Fastest and Most Effective Solution for DRC, Timing and Leakage Power Closure

Tutorial: Easing Floorplanning with Data Flow Analyzer

Tutorial: An Integrated Approach to Designing the Right SoC Architecture, Starting Software Development and SoC Validation Earlier Using Prototyping


Tutorial: Pre-route Layer Optimization and Correlation To Post Route

5:00-5:15 Best Paper Awards & Lucky Draw! - Olivia Ballroom Level 4