Conference at a Glance

SNUG Silicon Vallley | March 25-27, 2013

Monday, March 25, 2013
Tuesday, March 26, 2013
Wednesday, March 27, 2013

Monday, March 25, 2013



7:30-8:45 Registration and Breakfast
9:00-10:30 Welcome: Jonah Probell, SNUG Silicon Valley Technical Committee Chair

Keynote Address: Massive Innovation and Collaboration into the "GigaScale" Age!
Aart de Geus, Chairman and co-CEO, Synopsys, Inc.
10:30-11:00 Break

Implementation 1

Implementation 2

Implementation 3

Verification 1

Verification 2

STA & Extraction


Circuit Simulation




MA01 - IC Compiler 2013

IC Compiler 2013.03 Release Highlights

MA02 - Challenges and Strategies for Advanced Designs

High Performance SoCs: Effective Strategies for Achieving Optimal Performance, Power & Faster Design Closure

Routing at 20nm - It is Challenging but Achievable

MA03 - IC Compiler Custom Co-Design

IC Compiler Custom Co-Design

MA04 - Verification with OVM/UVM Methodologies

Reset Testing Made Simple with UVM Phases

OVM/UVM Scoreboards - Fundamental Architectures


MA06-A "No Man's Land" - Constraining Async Clock Domain Crossings

Winner, Technical Committee Award Technical Committee Award

MA06-B Efficient Timing Constraint Analysis and Debug using PrimeTime-GCA

Technical Committee Award
Honorable Mention Technical Committee Award

MA07 - FPGA-Based Prototyping

My BFF FPGA-Based Prototyping Solution: Better, Faster, and Flexible

MA08 - AMS for FinFET and 3DIC

Planar MOSFET to FinFET: A User Experience With HSPICE, FineSim, StarRC, RAPID3D, RC3

A New SPICE Simulation Approach for 3D IC Integration

MA09 - Hardening CPUs for Performance and Power

Hardening CPUs for Performance and Power with DesignWare Logic Libraries and Embedded Memories

12:30-2:00 Networking Lunch
12:30-2:00 MA10 - IP Lunch and Learn: Designing IP for FinFET Technology: The Opportunities and Challenges

MB01 - ARM GPU Implementation at 20nm

Proving the 20nm Implementation Ecosystem Using an ARM Mali GPU with a Full Galaxy Tool Flow

MB02 - Advanced CTS Methodologies

Holistic Clocking Methodology that Supports Low-Skew (<20ps) and High-Speed (>1.5GHz) Clocking with Low Power for 28nm Designs

Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler

MB03 - Design Compiler Update

Galaxy RTL: Design Compiler Family 2013.03 Update

MB04 - Debugging with Verdi

Verdi Transaction Based Debugging for SoC Designs

MB05 - Measuring and Improving Verification Quality

Functional Signoff: A Process for Measuring and Improving Verification Quality to Ensure Bug-Free Designs

MB06 - Optimizing Extraction Performance and Accuracy

Optimizing Extraction Performance: Samsung Success with StarRC Simultaneous Multi-Corner Extraction

Fast Extraction and Accuracy for Advanced 20nm and 14nm Designs

StarRC Transistor-level Extraction: Optimizing Accuracy and Performance for Custom AMS Flows

MB07 - Bringup and Debug of FPGA based Prototypes

Pest Control, Hunt Down Bugs Like the Experts


MB08-A Using IBIS-AMI Models in HSPICE

MB08-B Top-Down Post Full-Chip Verification for SRAM Boundary Simulation with FineSimPro

MB09 - 20nm Mixed-Signal IP - A Stepping Stone to 16nm FinFET?

20nm Mixed-Signal IP - A Stepping Stone to 16nm FinFET?

MB10 - Title Custom Designer Workshop

IC Compiler Custom Co-Design Workshop

3:30-3:45 Break

MC01 - Place and Route Vision Session

Advances in Place-and-Route Technology


MC02-A Floorplanning and Layout Feasibility with Multi-Instance Partitions

MC02-B Achieving Predictable Timing in ASIC Flow using Design Compiler Graphical/IC Compiler for High Performance Designs


MC3-A Hardware Redundancy and Design Fault Tolerance and their Applicability to Chip Design

MC3-B Synthesizing SystemVerilog: Busting the Myth that SystemVerilog is only for Verification


MC04-A VISA: A State-Based, Hierarchical, Architecture-Independent Random Test Generation Environment for High-Performance Multiprocessors

MC04-B Random Stability in SystemVerilog

MC05 - UVM Best Practices

UVM Best Practices

MC06 - Extraction for New Transistor Nodes and Technologies

Double Patterning Aware Extraction Flows For Digital Design Sign-Off in 20/14nm

Planar MOSFET to FINFET: A User Experience With HSPICE, FineSim, StarRC, RAPID3D, RC3

MC07 - Hybrid Prototyping

Hybrid Prototyping 101

MC08 - Circuit Simulation Release Update

Getting ready for the next technology node

MC09 - DDR Controller and DDR3/2 PHY IP

Integration of Synopsys' DesignWare DDR Controller & DDR3/2 PHY IP in 28nm

MC10 - IC Compiler Custom Co-Design Workshop

IC Compiler Custom Co-Design Workshop

4:00-8:00 Designer Community Expo

Tuesday, March 26, 2013



8:00-9:00 Registration and Breakfast
9:00-10:00 Technology Keynote - "From Crystal Ball to Reality — The impact of Silicon IP on SoC Design"
Sir Hossein Yassaie, PhD, Chief Executive Officer, Imagination Technologies Group
10:00-10:30 Break

Implementation 1

Implementation 2


Verification 1

Verification 2



Circuit Simulation




TA01 - FinFET Panel

FinFET Technology and Early Experiences


TA04-A Transaction Based Assertion for Transaction Level Coverage, Property and Protocol Checking

TA04-B Sub-cycle Functional Timing Verification using SystemVerilog Assertions

TA05 - Synopsys Discovery VIP

TA06 - Maximizing Signoff Productivity

PrimeTime HyperScale - Hierarchical STA

Simultaneous Multi-Voltage Analysis for Faster Timing Signoff

TA07 - Network Software Development using Virtual Prototypes

Ease Debug and Control of Network Software Using Virtual Prototypes to Do Full System Simulation

TA08 - Verification using Verilog-AMS

Analog and Mixed-signal Verification Methodology Using Verilog-AMS

TA09 - Implementing 10G Backplane Systems

Achieving Predictable and Highly Reliable 10G Backplane Designs

12:00-1:30 Networking Lunch
12:00-1:30 TA10 - Lunch and Learn: Design Compiler — Overcoming the Challenges of Shrinking Design Schedules vs. Increasing Complexity
12:00-1:30 TA11 - Lunch and Learn: Optimization exploration of ARM® Cortex™ Processor-based Designs with the Lynx Design System

TB01 - Implementation Flows for ARM Cortex-A7 and Cortex-A15 Cores

Power-Centric Timing Optimization of an ARM® Quad Core Cortex™-A7 Processor

Engineering Trade-Offs in the Implementation of a High Performance Dual Core ARM® Cortex™-A15 Processor

TB02 - Physical Verification of a Production FinFET SoC with IC Validator

Advancements in Density Management at 20nm and below with IC Validator

FinFET Physical Verification of Production Designs with IC Validator

TB03 - Meeting Test Quality Goals

Meeting Quality Goals for Gigascale Designs: Trends and Solutions


TB04-A Challenges with Design and Verification of State Retention in a Complex Low-Power SoC

TB4-B Formal Verification of Floating-Point Arithmetic Datapath Block

TB04-C A Reusable Verification Testbench Architecture Supporting C and UVM Mixed Tests

TB05 - Integrating Virtual Platforms into Hardware Accelerated RTL

Introduction to Integration of Virtual Platform Technologies with Hardware Accelerated RTL

TB06 - Leakage Recovery with PrimeTime

Signoff Driven Timing Closure with PrimeTime: Now Includes Leakage Reduction

Leakage Recovery across Multiple Timing Scenarios

TB07 - SoC Architecture Optimization

Low Power Video Processing for the Mobile SoC: How Analysis of HW-SW Partitioning Gets the Most from Embedded GPUs

SoC Architecture Analysis and Optimization Using Synopsys Platform Architect MCO


TB08-A A Practical Look at Current Analysis in FastSpice

TB08-B Transistor Level Static Circuit Analysis to Tackle ERC & ESD Challenges


TB09-A Deriving Timing Budgets for DDR4 Interfaces

TB09-B In the Cloud with PCI Express IP

TB10 - Synopsys Discovery VIP Workshop

Accelerating SoC Verification Using Discovery AXI™ VIP and AXI Interconnect Model

3:30-3:45 Break


TC01-A Advanced Retention Power Gating: Unlocking Opportunistic Leakage Savings in High Performance Mobile SoCs - Technical Committee Award, Honorable Mention Technical Committee Award

TC01-B Panel - Achieving Optimum Results on High Performance Processor Cores

TC02 - Design Environments using Lynx

Using the Lynx Design System to Lower the Cost of Bringing up a New Flow on a New Node

Standardized Design Environment and Methodologies Enable Simultaneous Implementation of 28nm Designs on a Single Flow

TC03 - Small Delay Defect Model and Advanced Debugging Test

Improving At-Speed Test Quality with the Small Delay Defect Model

Advanced TetraMAX Debugging Techniques for AMD's High-Performance Cores

TC04 - Transaction-level Verification with ZeBu-Server

Transaction-level Verification with ZeBu-Server - What, When, How

TC05 - Low Power Verification Debug

Can You Tell Your ISO from LS? - A Methodology for Low Power Debug

TC06 - Mode-Merging using PrimeTime

Using Mode-Merging to Reduce Scenarios Required for Timing Closure and Signoff

Automated Mode Merging of Timing Constraints using PrimeTime

TC07 - Power Management Software Development using Virtual Prototypes

Using Virtual Prototypes for the Early Bring-Up and Test of Power Management Software

TC09 - Increasing ARC Performance and Reducing Power

Increasing Performance and Reducing Power through Memory Request Optimization

TC10 - Synopsys Discovery VIP Workshop

Accelerating SoC Verification Using Discovery AXI™ VIP and AXI Interconnect Model

4:45-7:00 SNUG Pub
4:45-7:00 PrimeTime SIG - Featuring PrimeTime ADV - Advanced Timing Technology
PrimeTime SIG Dinner Registration — Walk-ins are welcome.

Wednesday, March 27, 2013



8:00-9:00 Registration and Breakfast
9:00-10:00 Technology Keynote - "Collaborate to Innovate - A Foundry's Perspective on Ecosystem"
Dr. Cliff Hou, Vice President, Research & Development, TSMC
10:00-10:30 Break

Implementation 1

Implementation 2


Verification 1

Compute Infrastructure




WA01 - Advanced CTS Features and Methodologies

Achieving Higher Frequencies for Your Design with Early Clockgating Optimization and Comprehensive Useful Skew

WA02 - Custom Design Using Laker

Laker 3 Custom Layout System - "An advanced process node custom layout tutorial"

WA03 - STAR Memory System

Embedded Memory Test, Repair & Diagnostics: DesignWare STAR Memory System Updates

WA04 - VCS for Best Performance

VCS Core Technologies for Best Performance

WA05 - High Performance Computing

High Performance Computing for Silicon Design

WA06 - Noise Analysis

Digital->Analog Noise Detection (DANDy)

Transistor-Level Timing and Noise Analysis of Peripheral Logic of High Speed Memory Design

WA07 - Designing with Xilinx 7 Series FPGAs

The Essentials for an Integrated Synplify-Vivado Design Flow Targeting Xilinx 7 Series FPGAs

12:00-1:00 Networking Lunch

WB01 - Multi-Bit Banking Solution

Introduction of Multi-Bit Banking Solution

WB03 - Multi-Die Memory Test for 2.5D Interposer

Multi-Die Memory Test in a 2.5D Silicon Interposer-Based Design

WB04 - VCS for Best Debug

VCS Technologies for Best Debug and Analysis

WB05 - Managing and Optimizing Compute Infrastructure

HP's Common Engineering Environment for VLSI design

Advanced Load Balancing and Resource Sharing Solutions

WB06 - Characterization Solutions

SiliconSmart Flow for Characterization Production Runs

CCS Noise Characterization Solution

WB07 - Maximizing Productivity on Large FPGA Designs

Methodologies and Techniques for Maximizing Productivity on Large FPGA Designs

2:30-2:45 Break

WC01 - Compiler ECO Flows

IC Compiler ECO Flows for Minimal Physical Impact

WC03 - Physical Failure and Yield Analysis

Successful Volume Diagnostics in a Fabless/Foundry Ecosystem

WC05 - Storage Optimization

VCS Acceleration Enabled by Storage Optimization

WC06 - Memory and Custom Digital Block Analysis and Characterization

Analysis and Characterization of Memories and Custom Digital Blocks using NanoTime

WC07 - Synthesis Methods for FPGA-Based Prototyping

Synthesis Methods for FPGA-Based Prototyping

4:15-5:00 Awards and Wrap Up