Conference at a Glance

SNUG France | June 11, 2013

Tuesday, June 11, 2013



8:30-9:30 Registration and Breakfast
9:30-10:30 Welcome and Introduction:
Pierluigi Daglio, STMicroelectronics and SNUG France Technical Chair

Keynote by Chi-Foon Chan, President and Co-CEO, Synopsys, Inc.

10:30-10:45 Break

Front-end Implementation

Digital and Low-Power Verification

Physical Design and Sign-off

Design for Test and Yield Analysis

FPGA and System

AMS Design and Verification

AMS Co-Design


A1 - Functional ECO Automation & UPF Implementation

Leveraging Formality ECO Flow to Speed up Last-Minute Change Verification

Taking Advantage of UPF2.0 for Advanced Low-Power Techniques

Converting an Outdated Library for UPF Compliancy Prior to a Low-Power Physical Design that uses Retention Flip-Flops

A2 - Accelerating SoC Verification

"Coverage-Driven" ASIC Verification Environments Coupled to an SQL Database

Accelerating SoC Verification with Synopsys Discovery VIP and the ARM CCI-400 Cache-Coherent Interconnect

A3 - Advanced Topics for Design Closure

Advanced CTS Techniques for High-Performance Mobile Designs

28nm FDSOI Leakage Optimisation with Synopsys Flow

Light Advanced on Chip Variation Approach

A4 - Design for Test and ATPG

Reducing the Tester Resources using Shared IO for a Quad-Core OpenGL ES GPU

Gate-Level DFT Flow Based on Synopsys Tool to Ease IP Reuse in Complex SOC

Using At-speed Testing with OCC (On Chip Clock Control) on a Complex SoC, a User Experience

A5 - Advanced Techniques for Multi-FPGA Prototyping

Prototyping a Large Multi-CPU SoC onto Multi-FPGA Boards using Certify Pin Multiplexing Techniques

Hardware/Software Transaction-Based Verification using the HAPS UMRBus

FPGA-Based Prototyping Solution: Better, Faster, and Flexible

A6 - Analog-Digital Co-Simulation

Improve IC-Level Verification Coverage by using Assertions with CustomSim-VCS Multi-Thread Real Number Flow

"Digital Supplies are Analog!" - CustomSim-VCS with UPF

12:15-13:30 Networking Lunch

B1 - Managing Constraints & Lynx Flow

Minimizing Risk in Multi-clock Designs with GCA

GCA -Based Methodology to Check Quality of Scan Shift Constraints

Improve Design Quality with Efficient Design Exploration in Lynx Design System

B2 - Advanced IP Verification

Regression Performance Optimization of a Full HD-120fps Video Encoder Based on VCS Multi-Core Functionality

UVM-based Power Aware Platform for Multicore Sub-system Verification

Low-Power Verification using Power State Table Coverage

B3 - Closure and Signoff

Using PrimeRail for Advanced Microcontroller Dynamic IRdrop Analysis

IC Compiler ECO Flows for Minimal Physical Impact

B4 - Improving Test Quality and Yield

Delay Faults Detection in Synchronous Clock Domain Logic

Non Scan Logic Handling in a Full Digital Design

Volume Diagnostics on Slack-based Transition Test Patterns to Improve Yield of a Slow Process

B5 - FPGA-Based Prototyping Methodology

ASIC to FPGA RTL Prototyping using Synplify Tools

Complex Mobile Multi-Media SoC Prototyping using Xilinx Virtex 7-based HAPS-70 Systems

Methodologies and Techniques for Maximizing Productivity on Large FPGA Designs

B6 - Advanced AMS Verification

Aging Model Implementation using MOSRA API Flow from HSPICE to CustomSim (XA) FastSPICE: Applications at STMicroelectronics

The Art of Reliability: Guidelines to Reduce IR-drop and Electro-Migration Effects in Full Custom Designs

Circuit Check Extension to Optimize ERC Flow, User Experience, Guidelines for Expert and Novice Users

B7 - AMS Co-Design

IC Compiler Custom Co-Design Workshop

15:00-15:30 Break

C1 - Low-Power Full Flow

Introduction of Multi-Bit Banking Solution

Power-Centric Timing Optimization Flow for an ARM® Cortex™-A7 Quad Core Processor

C2 - Improving Debug Methodology

Debug Hints and Tips using Verdi3 and DVE

Kalray's Advanced Debug Flow using Synopsys Verdi and Certitude Solution

C3 - Physical Implementation

Concurrent Top and Blocks Level Implementation of a High-Performance Graphics Core using One-Pass Timing Closure in Synopsys ICC

Advanced Technologies FRAM View Generation Methodology

IC Compiler 2013.03 Release Highlights

C4 - Advanced Techniques for Test and ATPG Pattern Simulation

Meeting Quality Goals for Gigascale Designs: Trends and Solutions

R&D Q&A Session - Accelerate ATPG Pattern Validation

C5 - Emulation, Transaction-Based Verification and Virtual Prototyping

Redefining the Emulation Landscape for the Latest SoC Challenges with Zebu Server

Fast Deployment of Zebu to Perform SW Verification & Development Before Silicon

Using Virtual Prototypes for the Early Bring-Up and Test of Power Management Software

C6 - Advanced AMS Verification and Custom Design

An Accurate Path Verification to Secure and to Speed Up Nanometer Design Closure

Full Front-to-Back Custom Design Flow: "The Power of Custom Designer-SE & Laker"

The tutorial is followed by a Customer Testimonial

17:00-18:00 Awards and Refreshments