Synopsys' FPGA-based ZeBu emulators hold the promise of extremely high execution speed, and enable the verification of system-level scenarios that require billions of execution cycles. For large ASIC designs, the key to RTL synthesis for emulation is quickly producing an emulation-friendly netlist that is debug-friendly. zFAST (ZeBu Fast Synthesis) is a Xilinx® Virtex® FPGA synthesis tool from Synopsys, specifically targeted for use with ZeBu emulators, and supporting SystemVerilog, Verilog, VHDL, and mixed language designs. zFAST is fully integrated into the Synopsys toolset, and enhances ZeBu emulation by providing extremely fast parallel and incremental synthesis, support for non-synthesizable constructs and memory inference, and enabling greater debug capabilities.
Download the zFAST Datasheet.
- 10X to 20X faster than traditional synthesis tools
- Supports Full and Block Synthesis Modes, Parallel and Incremental Synthesis
- Supports SystemVerilog, Verilog, VHDL and mixed language designs
- Supports User Defined Primitives (UDPs), automatic memory inferencing and Synopsys DesignWare® Foundation Library Components
- Enhanced debugging with support for synthesizable SystemVerilog Assertions (SVA);, RTL name preservation; preload, read and write support for inferred memories
- Efficient use of FPGA and emulator resources
- Comparable area to traditional FPGA synthesis (-10% to +25%)
- Emulation speed equivalent to traditional FPGA synthesis
- Fully Integrated with ZeBu Compiler and Runtime environment
- Interoperable with traditional FPGA synthesis tools
Product: ZeBu Debug