Verification 

High-Performance, Scalable SoC Verification and Software Bring Up 

Synopsys Verification Continuum is a comprehensive verification platform built from the industry’s fastest engines for virtual prototyping, static and formal verification, simulation, emulation, FPGA-based prototyping and debug. Verification Continuum features Unified Compile based on VCS for a simulation-like use model throughout the verification flow, enabling faster design bring-up, seamless transitions between simulation, emulation and prototyping. It also delivers Unified Debug with Verdi to provide a debug continuum across all domains and abstraction levels enabling dramatic increases in debug efficiency. The Synopsys Verification Continuum also includes comprehensive planning and coverage as well as a multi-platform, verification IP solutions. This platform is collectively complemented by low power and analog/mixed-signal technology, integration and flows.

 

Verification Compiler
Comprehensive, best-in-class verification in one product
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VCS
High-performance verification, new multicore technology


VCS AMS
Mixed-signal verification solution


VCS Native Low Power (NLP)
Voltage-aware native low power simulation
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Verification IP
Synopsys Verification IP Protocols


SpyGlass
Early SoC design analysis technology


VC LP
Advanced low power static rules checker solution
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VC Formal
Next-generation formal verification solution
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VC Formal Coverage Analyzer
Integrated formal analysis for coverage closure



ZeBu Server
Billion-gate ASIC and SoC acceleration and emulation


Certitude
Functional qualification system
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HECTOR
Next-generation formal block-level consistency checker


BugScope
Improved functional verification for RTL designers


VCS AMS
Mixed-signal verification solution


Circuit Simulation
Performance, accuracy and capacity for AMS verification


Reliability & Circuit Checks
Transistor-level reliability analysis and electrical violation checking


Waveform Analysis & Debug
Avoid wasted simulation time, better mixed-signal chips...faster!


Custom Extraction
Unified gold-standard extraction to accelerate custom IC design


SpyGlass
Early SoC design analysis technology


VC LP
Advanced Low Power static checking solution
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VC Formal
Next-generation formal verification solution
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VC Formal Coverage Analyzer
Integrated formal analysis for coverage closure



Formal Equivalence Checking
Comprehensive equivalence checking


HECTOR
Next-generation formal block-level consistency checker

  • Debug
  • Open debug solutions for design and verificationmore

Verdi
Automated debug system
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Siloti
Visibility automation system
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ProtoLink
Probe visualizer
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VIP that accelerates run-time, debug and coverage closure for SoC designs


 
High-performance SoC emulation systems help engineers find hardware and embedded software bugs fast, shortening time-to-silicon


 
Improves time-to-market and helps avoid costly device re-spins by enabling early embedded software development and allowing HW/SW co-design well ahead of chip fabrication.


 
Synopsys' virtual prototyping solution includes the Virtualizer tool set and the industry's largest portfolio of transaction-level models.

Key Benefits
  • Industry’s fastest engines for virtual prototyping, static and formal verification, simulation, emulation, FPGA-based prototyping and debug
  • Unified Compile with VCS for a simulator-like use model throughout the verification flow
  • Unified Debug with Verdi with a consistent debug user experience across multiple engines for 3X productivity
  • Architected to support high-performance, scalable FPGA-based emulation and prototyping systems

Verification Challenges
Mobile and Internet of Things (IoT) markets are driving dramatic increases in SoC complexity and software content, and intensifying pressure on time-to-market. To address these challenges, SoC teams require many verification technologies such as simulation, emulation and prototyping across the spectrum of pre-silicon verification, post-silicon validation and software bring-up. Today, it takes months of design bring-up and transition effort between disjoint technologies, further complicated by the need to debug across domains and to support large software teams.

Leading teams are adopting "shift-left" strategies with concurrent practices across pre-silicon verification, post-silicon validation and software bring-up to SoC shorten time-to-market. Synopsys’ Verification Continuum enables these shift-left strategies with best-in-class verification technologies unified with seamless design bring-up, transition and debug throughout the flow.



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