Sep 19, 2016Synopsys Accelerates Development of Safety-Critical Products with Design Solutions for ARM Cortex-R52
Synopsys Tools Enable Design and Safety Certification of Automotive, Industrial and Health Care SoCs Based on New ARMv8-R Architecture CPU

May 02, 2016Synopsys Delivers Next-Generation Verification IP for Micron’s Hybrid Memory Cube Architecture
Native SystemVerilog VIP Enables Ease of Development for HMC Solutions

Apr 13, 2016Synopsys Delivers Industry’s First Verification IP for USB Power Delivery 3.0
Native SystemVerilog VIP Features Built-in Coverage, Verification Planning, Protocol-Aware Debug and Source Code Test Suites

Apr 05, 2016Synopsys Extends Verification IP Portfolio for Automotive Applications
Native SystemVerilog VIP and Source Code Test Suites for CAN 2.0/FD/TT, LIN, FlexRay and Ethernet AVB

Mar 29, 2016Synopsys Accelerates RTL Signoff with Introduction of New SpyGlass Lint Advanced Solution
Breakthrough Lint-Turbo Technology Delivers 10 Performance, 5X Improvement in Memory, and 3X Faster Design Closure

Mar 24, 2016Synopsys Unveils Breakthrough Parallel Simulation Performance Technology for VCS
Cheetah Fine-Grained Parallelism Technology Enables up to 5X RTL and 30X Gate-level Simulation Acceleration

Mar 02, 2016Synopsys Extends Leadership in Functional Safety and Security Verification with Addition of Key Technology for ISO 26262 Compliance
Acquires Leader in Fault Simulation

Feb 24, 2016Synopsys Accelerates Verification Closure of Multimedia SoCs with Next-Generation Verification IP for HDMI 2.0a and HDCP 2.2
Native SystemVerilog HDMI VIP Includes Built-In Coverage,Verification Planning and Protocol-Aware Debug

Feb 23, 2016Synopsys Delivers Unified Analog and Mixed-Signal Debug with Verdi Advanced AMS Debug Solution
Extends Verdi's Market-Leading SoC Debug Platform with Comprehensive and Automated AMS Debug Capabilities

Feb 03, 2016Synopsys Redefines Circuit Simulation with Native Environment
Eliminates Need for Third-party Environment, Accelerates Analog Verification

Feb 01, 2016Synopsys Delivers Industry's First SAS 24G Verification IP for Enterprise Storage Systems
First Verification IP Product Line That Includes All SAS Interface Speed Configurations

Nov 23, 2015Synopsys Delivers Industry's First Ethernet 400G Verification IP for Next-Generation Networking and Communications Systems
Native SystemVerilog Ethernet VIP Features Built-in Coverage, Verification Planning, Protocol-Aware Debug and Source Code Test Suites

Nov 10, 2015Synopsys Enables Next-Level of Productivity with Addition of System-Level Capabilities to Verification IP for ARM Cache Coherent Protocols
Expands Comprehensive VIP library for ARM® AMBA® protocols with System-Level Test Suites, System Monitor, Protocol-aware Debug and Performance Analysis; Adds VIP for New AMBA 5 AHB5 Standard

Nov 03, 2015MEDIA ALERT: Synopsys, Customers and Partners Highlight Successes Designing ARM-based Products at ARM TechCon 2015
Technical Sessions Feature Processor Optimization, IP, Software Security, Prototyping and Verification Solutions

Jun 08, 2015Synopsys' CustomSim Delivers 2X Circuit Simulation Speed-up
New Partitioning Technology Enables Consistent Multi-core Scalability

May 13, 2015Synopsys' Verification IP for DDR4 3DS Enables DRAM Designs with Higher Density and Performance at Reduced Power
Native SystemVerilog-based VIP for DDR4 3DS Expands Synopsys' Portfolio of Memory VIP and Offers Built-in Coverage, Protocol Checks, Verification Plan and Protocol-aware Debug

Mar 17, 2015Synopsys Enables Continuous Debug Innovation with More Than 200 VC Apps Now Available on the Verdi Platform
Synopsys how has more than 200 debug and analysis apps available on the VC Apps Exchange portal and in the Verdi® VC Apps Toolbox, demonstrating rapid momentum for customized applications that drive continuous innovation and further enable system-on-chip (SoC) teams to address their debug challenges.

Mar 12, 2015Synopsys' New Verification IP for MIPI SoundWire Enables Audio and Control Interfaces in Low Power Designs
Native SystemVerilog-based VIP for SoundWire Expands Portfolio of VIP for Mobile Applications and Offers Built-in Coverage, Verification Plan and Protocol-aware Debug

Mar 12, 2015Synopsys Continues to Sell, Ship and Support ZeBu Emulation Systems Worldwide
With new release that does not include older technology and includes 3X faster compile technology, Synopsys expects to gain emulation market segment share

Feb 06, 2015ARM and Synopsys Collaborate On ARM Cortex-A72 Processor-based SoCs with IC Compiler II
ARM and Synopsys Collaboration Enables Optimized Implementation of ARM Cortex-A72 Processor-based SoCs with IC Compiler II

Feb 03, 2015Synopsys’ New 25G/50G Ethernet Verification IP Enables Next-Generation Gigabit Designs
Native SystemVerilog Ethernet VIP and Source Code Test Suites Enhanced with Built-in-Coverage and Support for Protocol-aware Debug

Jan 21, 2015Synopsys Expands Memory Verification IP Portfolio with UFS, UniPro and eMMC to Accelerate Verification Closure for Mobile Designs
Expands Memory Verification IP (VIP) Portfolio to Include Key Titles for the Mobile Industry

Oct 27, 2014SK Hynix Accelerates Memory Development with Productivity-Enhancing Debug Apps on Synopsys Verdi
VC Apps open APIs automate memory testbench generation and debug. SK Hynix, Inc. has addressed their debug challenges by adopting the Synopsys VC Apps open application programming interfaces (APIs) to directly link their internally developed test generation technology to the industry-leading Synopsys Verdi® debug solution and allow their design and verification teams to customize their debug experience and boost debug productivity.

Oct 14, 2014Synopsys Enables Superior Verification Planning and Coverage Analysis with Verdi Coverage
Verdi Coverage enables users to understand project progress, manage regression data, launch verification jobs, track project trends, generate reports and ultimately optimize resource allocation. This solution addresses the growing challenge of verification closure for complex system-on-chips (SoCs) by introducing advanced technology that allows users to quickly create efficient verification plans, integrate third-party and user-defined metrics, link plans to requirement documents, and intuitively track project and test-level metrics across simulation, static checking, formal verification, VIP and FPGA-based prototyping.

NewsArticlesBlogsSuccess StoriesWhite PapersWebinarsVideosTraining Courses