SATA Verification IP 

 

Overview
The Serial ATA (SATA) System Verification Component (SVC) is designed to verify SATA-based designs using both random and directed simulation. The SATA SVC supports constrained randomization parameters throughout the layers to aid in achieving coverage during verification. The SVC is verification methodology neutral, and can be integrated with and controlled by any hardware verification language (e.g. SystemVerilog, UVM, C / C++, Vera, Specman, or Verilog). The SATA SVC supports all popular simulators.

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Primary Features
  • SATA Gen 1, 2, and 3 plus extensions
  • Includes both host and device models
  • Supports all SATA commands (PIO, DMA, LCQ, NCQ, Send / Receive FPDMA Queued)
  • Can be used at any link speed including 6 Gb
  • Support for interrupt aggregation
  • OOB sequence generation and checking
  • Includes digital SERDES model with receiver clock recovery
  • Scalable for multiple instantiations in a test bench (for testing multi-port hosts)
  • Configurable pattern generation for random, directed or erroneous patterns
  • Includes transactor interfaces for directed testing
  • Includes constrained-randomized parameters to aid in coverage during randomized testing
  • Checkers verify protocol timing checks and functional accuracy at each layer
  • Support for power management modes (Partial, Slumber, Devslp)
  • Supports all major simulators



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