Discovery Verification IP for I2S 

 

Overview
Synopsys Discovery™ Verification IP (VIP) for I2S supports verification of designs that include interfaces implementing the I2S specification. Discovery VIP for I2S is integrated with the Discovery Protocol Analyzer, a protocol-aware debug environement that enable users to quickly debug protocols by raising the abstraction level, and providing easy navigation through layers of the protocol hierarchy. Discovery VIP for I2S includes a comprehensive set of protocol, methodology, verification, coverage and ease-of-use features to enable rapid verification of I2S interfaces. Discovery VIP for I2S is written entirely in SystemVerilog enabling it to run natively in supported simulators for highest performance. Its SystemVerilog architecture includes built-in support for UVM, OVM and built-in functional coverage. Built-in coverage points integrate with the verification plans to show progress towards achieving coverage goals.

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Discovery Verification IP for I2S

Primary Features
  • Fully compliant with the I2S bus specification, revision June 5, 1996.
  • Full and half duplex
  • Configurable frame lengths for different (audio) transfer rates
  • Configurable as master or slave
  • Dataword length upto 64 bits
  • Built-in functional coverage (toggle, transaction coverage)
  • Protocol checks
  • Debug port
  • Multi agent system env
  • Transmitter and receiver agents can be used in standalone mode
  • Callbacks for transmitter/receiver agents
  • Supports UVM and OVM testbench
  • Supports all major simulators



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