I2C Verification IP 

 

Overview
The Discovery™ Verification IP (VIP) for I2C provides support for I2C version 2.1, including all speeds. With a comprehensive set of protocols, methodology, verification and ease-of-use features, users are able to achieve rapid coverage convergence for their I2C designs. Discovery VIP for I2C is integrated with the Discovery Protocol Analyzer, a protocol-aware debug environment that enables users to quickly debug protocols by raising the abstraction level, and providing easy navigation through layers of the protocol hierarchy. Discovery VIP for I2C is written entirely in SystemVerilog enabling it to run natively in supported simulators for highest performance. Its SystemVerilog architecture includes native support for UVM and built-in functional coverage.

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Discovery I2C Verification IP

Figure 1: Discovery I2C Verification IP

Primary Features
  • All features of I2C version 2.1
  • Fast-mode plus speed feature of version 3.0
  • Standard-mode, fast-mode, fast-mode plus, and high-speed mode
  • Supports both 7-bit and 10-bit addressing
  • Includes master agent and slave agent
  • Slave agent can be configured as a generic slave or as an EEPROM slave
  • Includes monitor and checker
  • Analysis ports to connect master or slave agents to scoreboard
  • Built-in verification plan
  • Built-in protocol checks
  • Built-in functional coverage
  • Supports Protocol Analyzer
  • Supports System Verilog UVM, OVM testbenches
  • Supports all major simulators



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