Verification Seminars Series 2014 

Enabling 3x Verification Productivity   

Seminar Overview
The Verification Seminar is a one-day technical seminar providing an overview of Synopsys’ functional verification technologies and how the recently introduced Verification Compiler offers key technologies and capabilities to help manage verification complexity. The seminar will also delve into several advanced verification flows comprising Synopsys technologies, including static and formal verification, simulation, advanced debug, coverage-driven verification, verification IP, emulation, and FPGA prototyping.

Who Should Attend
Verification engineers and managers

Seminar Agenda
(may vary in some locations)

Overview: Synopsys Verification Direction

Introduction to Verification Compiler

  • 3x Productivity with Verification Compiler
  • Planning for success and optimizing Coverage-Driven Verification
  • Early bug finding using Static and Formal technology
  • Low Power Verification
  • Verification IP and Memory Models
  • Advanced debug

Advanced Flows

  • Analog/mixed-signal debug and analysis
  • Performance analysis, HW/SW Debug, Integration with Virtual Platforms
  • HW/SW Bring-up and Emulation
  • FPGA Prototyping

Note: Lunch will be provided.

Verification Seminar Schedule

May 6, 2014 Irvine, CA Completed
May 14, 2014 Hsinchu, Taiwan Completed
May 16, 2014 Shanghai, ChinaCompleted
May 20, 2014 Shenzhen, ChinaCompleted
May 22, 2014 Beijing, ChinaCompleted
June 12, 2014 Marlborough, MACompleted
July 9, 2014 Austin, TXCompleted
July 10, 2014 Seoul, KoreaCompleted
August 12, 2014 Toronto, Canada Completed
August 14, 2014 Ottawa, Canada Completed
August 27, 2014 Boulder, CO Completed
September 17, 2014 Columbia, MDCompleted
October 1, 2014 Dublin, IrelandCompleted
October 9, 2014 Bristol, EnglandCompleted
October 16, 2014 Eindhoven, The NetherlandsCompleted
October 23, 2014 Reading, EnglandCompleted

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