Programmable Netlist-Driven Transistor Level Design Checker 

SpiceCheck is a programmable transistor-level netlist-driven static design checker. The check functionality is fully customizable based on a rich set of Tcl check commands. The program accepts flat and hierarchical netlist input and allows access to design properties including device parameters, process models, design connectivity and power domain information.

The efficient static approach in SpiceCheck helps designers quickly identify critical multi-supply design issues such as missing level-shifters and isolation gates. The programmable environment allows the check functions to be easily adapted to different design styles and disciplines. Additionally, the waveform processing capability in SpiceCheck facilitates complex design analysis using results from dynamic simulations.

For post-layout verification applications, SpiceCheck is also capable of correlating extracted parasitics to the original ideal design; finding critical parasitic elements; and calculating total resistance along parasitic network.

SpiceCheck Function Overview
  • Design traversal with flexible selective access
  • Full access to device and net properties
  • Inquiry of design connectivity
  • Static DC power domain estimation
  • Automatic netlist-driven topology finder
  • CMOS signal path tracing
  • Correlation between extracted and ideal netlist
  • Total parasitic resistance calculator
  • Cross-reference to dynamic waveforms
  • Interactive check result browser

Figure 1: Example SpiceCheck procedure
Figure 1: Example SpiceCheck procedure

Common SpiceCheck Application
  • Irregular device sizing and floating terminals
  • NMOS on power rail, PMOS on ground rail
  • Device over-biased or in wrong power domain
  • Missing level-shifters and isolation gates
  • Missing ESD cells at I/O pads
  • IP cells screening for missing I/O buffers
  • Auto search for critical circuit topology
  • Critical parasitic resistance path
  • Automated waveform measurement extraction
Supported Design Environments
  • Synopsys : HSPICE®
  • Cadence Design : Spectre®
  • Mentor Graphics : Eldo
  • Standard Spice

Figure 2: SpiceCheck capabilities
Figure 2: SpiceCheck capabilities

Figure 3: SpiceCheck development environment
Figure 3: SpiceCheck development environment

Programming Environment
  • Programming language: Tcl
  • Batch or interactive mode operations
  • Loadable Tcl package for use with Tcl debuggers
O/S and Platform Supports
  • Unix : Solaris / HP-UX 11, 32/64-bit O/S
  • Linux : Enterprise 3

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