|Oct 01, 2013||Why does EUV Matter?|
Lithography represents the greatest challenge to the continuation of Moore’s Law in its history. Even EUV won’t solve all problems.
|Sep 19, 2013||Mask Data Prep Issues Compounding at 20nm|
Preparing a design to be printed at the mask shop has become increasingly more complex. Dealing with those issues requires embracing new technologies to prep a design.
|Feb 25, 2013||MagnaChip Selects Synopsys' Proteus LRC for Lithography Verification|
Synopsys today announced the adoption of Synopsys' Proteus™ LRC by MagnaChip Semiconductor Corporation, a Korea-based designer and manufacturer of analog and mixed-signal semiconductor products. MagnaChip uses Proteus LRC in their production mask synthesis flow to identify hotspot locations in designs that are sensitive to variations in the manufacturing process.
|Jan 22, 2013||Synopsys Accelerates Adoption of FinFET Technology with Production-Proven Design Tools and IP|
FinFET Technology Support Developed over Five-year Collaboration with Industry Leaders
|Dec 12, 2012||Imec and Synopsys Expand FinFET Collaboration to 10 Nanometer Geometry|
Imec and Synopsys today announced that they have expanded their collaboration in the field of Technology Computer Aided Design (TCAD) to next-generation FinFET technology at 10 nm
|Nov 14, 2012||Synopsys and TSMC Enable Lithography Compliance Checking for 20nm|
Synopsys today announced the delivery of lithography compliance checking technology for the TSMC 20-nanometer (nm) DFM Data Kit (DDK) encapsulated with Synopsys?? Proteus mask synthesis technologies
|Nov 05, 2012||Synopsys Announces Adoption of its TetraMAX ATPG and Yield Explorer Tools by STMicroelectronics as Essential Enablers of Rapid Yield Ramp|
Synopsys' solution has enabled ST engineers to quickly identify the most dominant systematic failure mechanisms on new designs, thereby driving yield improvement at a faster rate.
|Jun 27, 2012||SSMC Selects Synopsys' Proteus LRC|
SSMC has deployed Proteus LRC in their production and development flows for post-OPC lithography verification to identify critical manufacturing hotspot locations that are sensitive to process variation and susceptible to increased yield loss.
|May 30, 2012||GLOBALFOUNDRIES Selects Yield Explorer for Faster Yield Ramp|
Unique Fabless-Foundry Sharing Model Allows Automated Volume Diagnostics to Identify and Prioritize Systematic Failure Mechanisms
|Apr 18, 2012||Renesas Adopts Synopsys' Proteus LRC for Lithography Verification|
Post-OPC Verification Solution Offers Lowest Cost of Ownership and High Accuracy
|Jan 03, 2012||Leading Memory Manufacturer Endorses Proteus LRC for Lithography Verification|
Post-OPC Verification Tool Provides Highest Accuracy and Lowest Cost of Ownership
|Mar 01, 2011||Synopsys Introduces Proteus LRC for Lithography Verification|
Proteus LRC provides comprehensive, process-window-aware checking features to identify locations in a design that are sensitive to process variations, thereby enabling corrective action to be taken prior to committing a design to manufacture.
|Oct 28, 2010||Carl Zeiss and Synopsys Collaborate on In-Die Registration Metrology for Photomask Manufacturing|
Carl Zeiss and Synopsys announce a collaboration to support the ZEISS tool family for in-die metrology solutions for the 32-nanometer (nm) technology node and below.
|Jul 13, 2010||SVTC Technologies Selects Synopsys' Manufacturing Tools to Accelerate Time to Commercialization|
SVTC Technologies has chosen Synopsys' manufacturing tool suite to enable its customers to reduce time-to-market for a wide variety of innovative products using CMOS processes, MEMS, photovoltaics and other related nanotechnologies.
|Mar 23, 2010||Renesas Technology Has Adopted Synopsys Proteus OPC for 28-nm Development|
The 28-nm node pushes the limits for single-exposure photon-based lithography, and by selecting Proteus, Renesas can achieve their aggressive OPC accuracy specifications with improvement of process robustness.
|Oct 28, 2009||NVIDIA Adopts Synopsys Yield Explorer to Reduce Time to Volume|
Design-centric yield management enables product engineers to achieve rapid yield ramp and provide cost-effective yield control in volume production
|Mar 16, 2009||Synopsys Announces Yield Explorer – Design-Centric Yield Management for Product Engineering Teams |
Yield Explorer Demonstrates 10x Faster Volume Diagnostics Analysis with a Single Data-Bank for Design, Fab and Test Data to Identify the Source of Yield Loss
|Feb 26, 2008||Synopsys Unveils Proteus Pipeline Technology, Delivering a New Level of Performance|
Synopsys Inc. today announced the capability to pipeline key manufacturing applications. The new pipeline technology delivers reduction in design-to-mask cycle time.
|Oct 23, 2007||Synopsys Customers Accelerate Yield Learning With Converged Test and Yield Management Data Flow|
Synopsys, Inc. today announced general availability of the Odyssey Design-for-Test (DFT) module for use by design organizations worldwide.
|Sep 18, 2007||Nikon and Synopsys Announce Manufacturing-Aware DFM Solution for 45 nm and Below|
Embedded Scanner Parameter Module Delivers Improved OPC Accuracy, Enhanced Model Predictability and Reduced Time to Silicon for Mutual Customers
|Sep 11, 2007||Voltaire and Synopsys Introduce High-Performance Compute Solution to Reduce Cycle Time for Semiconductor Mask Manufacturing|
Voltaire Ltd. today announced they are developing a high-performance compute (HPC) cluster solution for semiconductor mask data-preparation (MDP) applications.
|Jun 12, 2007||Synopsys and Hitachi High-Technologies Deliver Enhanced OPC Modeling Speed, Accuracy and Predictability|
Synopsys, Inc. today announced that they have developed a seamless link between Hitachi High-Tech's DesignGauge design data measuring system and Synopsys' Proteus optical proximity correction (OPC) solution.
|Feb 27, 2007||Synopsys Proteus OPC Delivers Superior Cost of Ownership on Intel® Core™ Microarchitecture|
Optimized x86-64 Hardware Offers Superior Price/Performance for OPC Compared to Custom Hardware Platforms