Synopsys at SPIE Advanced Lithography 2013 

 

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Synopsys Technical Forum

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Synopsys Technical Program at SPIE Advanced Lithography

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  • PDF3D resist profile modeling for OPC applications
    Paper 8683-43
    Author(s): Yongfa Fan, Synopsys, Inc. (United States); Koh K. Kit, Globalfoundries (China); Qing Yang, ; Wolfgang Hoppe, Bernd Kuechler, Synopsys GmbH (Germany); Puvan Perampalam, ; Makoto Miyagi, Synopsys, Inc. (United States); Thomas Schmöller, Synopsys GmbH (Germany)
  • PDF7nm node EUV predictive study of mask LER transference to CD variance
    Paper 8679-97
    Authors: Deniz Civay, Thomas I. Wallow, Yuansheng Ma, Harry J. Levinson, GLOBALFOUNDRIES Inc. (United States); Joachim Siebert, Eva Nash, Ulrich K. Klostermann, Synopsys GmbH (Germany)
  • PDFAvoiding wafer-print artifacts in spacer is dielectric (SID) patterning
    Paper 8683-37
    Authors: Gerard Luk-Pat, Benjamin D. Painter, Alexander Miloslavsky, Synopsys, Inc. (United States); Peter De Bisschop, IMEC (Belgium); Adam Beacham, Synopsys, Inc. (Canada); Kevin Lucas, Synopsys, Inc. (United States)
  • PDFCompact OPC model optimization using emulated data
    Paper 8683-30
    Authors: Artak Isoyan, Synopsys, Inc. (United States); Thomas Mülders, Synopsys GmbH (Germany); Lawrence S. Melvin III, Synopsys, Inc. (United States)
  • PDFDesign-based metrology for development and manufacturing applications
    Paper 8681-110
    Authors: Peter D. Brooker, Synopsys, Inc. (United States); Shimon Levi, Applied Materials (Israel); Sylvain Berthiaume, Synopsys, Inc. (Canada); William A. Stanton, Travis Brist, Synopsys, Inc. (United States)
  • PDFEvaluation of cost-driven triple-patterning lithography decomposition
    Paper 8684-7
    Authors: Haitong Tian, Univ. of Illinois at Urbana-Champaign (United States); Hongbo Zhang, Synopsys, Inc. (United States); Martin D. F. Wong, Univ. of Illinois at Urbana-Champaign (United States)
  • PDFThe impact of realistic source shape and flexibility on source-mask optimization (Coming Soon)
    Paper 8683-22
    Authors: Hajime Aoyama, Yasushi Mizuno, Noriyuki Hirayanagi, Nikon Corp. (Japan); Hiro Izumi, Keiichi Tajima, Nihon Synopsys G.K. (Japan); Joachim Siebert, Wolfgang Demmerle, Synopsys GmbH (Germany); Tomoyuki Matsuyama, Nikon Corp. (Japan)
  • PDFImproved SADP decomposition for SID process with model-based verification
    Paper 8684-13
    Authors: Yuelin Du, Univ. of Illinois at Urbana-Champaign (United States) and Synopsys, Inc. (United States); Hua Song, James P. Shiely, Synopsys, Inc. (United States); Martin D. F. Wong, Univ. of Illinois at Urbana-Champaign (United States)
  • PDFMask compensation for process flare in 193nm very low-K1 lithography
    Paper 8683-15
    Authors: Jeonkyu Lee, Taehyeong Lee, Chunsoo Kang, Jungchan Kim, Jaeseung Choi, Chan-Ha Park, Hyun-Jo Yang, Dong Gyu Yim, SK Hynix, Inc. (Korea, Republic of); Jung-Hoe Choi, Synopsys Korea Inc. (Korea, Republic of); Irene Su, Synopsys Taiwan Ltd. (Taiwan); Hua Song, Synopsys, Inc. (United States); Mun-hoi Do, Synopsys Korea Inc. (Korea, Republic of); Yongfa Fan, Anthony C. Wang, Synopsys, Inc. (United States); Sung-Woo Lee, Synopsys Korea Inc. (Korea, Republic of); Kevin Lucas, Synopsys, Inc. (United States)
  • PDFRole of 3D photoresist simulation for advanced technology nodes
    Paper 8683-49
    Authors: Aravind Narayana Samy, Rolf Seltmann, Frank Kahlenberg, Jessy Schramm, GLOBALFOUNDRIES Dresden Module Two, GmbH& Co. KG (Germany); Bernd Kuechler, Ulrich K. Klostermann, Synopsys GmbH (Germany)
  • PDFTriple patterning with polygon stitching: scalability and compliance for metal 1 at the 14nm node
    Paper 8683-7
    Authors: Christopher M. Cork, Synopsys SARL (France); Alexander Miloslavsky, Yong Li, Kevin Lucas, Synopsys, Inc. (United States)

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