White Papers 

Signoff-Driven Timing Closure ECO in the Synopsys Galaxy Platform - Simplified Chinese
This paper explains how the timing ECO flow delivers fast, predictable, signoff-driven timing closure in a single pass. It covers a new physically-aware architecture; which runs on a single machine or across compute farms, on designs with over 100 million instances, and reduces tapeout schedules by weeks during timing closure and signoff; one of the most critical phases of IC design.
James Chuang, Technical Marketing Manager, Synopsys

Signoff-Driven Timing Closure ECO in the Synopsys Galaxy Platform - Traditional Chinese
This paper explains how the timing ECO flow delivers fast, predictable, signoff-driven timing closure in a single pass. It covers a new physically-aware architecture; which runs on a single machine or across compute farms, on designs with over 100 million instances, and reduces tapeout schedules by weeks during timing closure and signoff; one of the most critical phases of IC design.
James Chuang, Technical Marketing Manager, Synopsys

Signoff-Driven Timing Closure ECO in the Synopsys Galaxy Platform
This paper explains how the timing ECO flow delivers fast, predictable, signoff-driven timing closure in a single pass. It covers a new physically-aware architecture; which runs on a single machine or across compute farms, on designs with over 100 million instances, and reduces tapeout schedules by weeks during timing closure and signoff; one of the most critical phases of IC design.
James Chuang, Technical Marketing Manager, Synopsys

PrimeTime Mode Merging – Reducing Analysis cost for Multimode Designs
As process technologies shrink, design teams can fit increasing amounts of logic in a single chip, combining functionality that was captured in the past by discrete devices. This increased functional complexity often accompanies more configurability, allowing portions of the logic to be selectively enabled, depending on the task being executed. Examples include a mobile chip that disables graphics processing logic when the display is not in use, or a multiprocessor configuration that can enable specific cores to complete a given processing task.
Ron Craig, Technical Marketing Manager, Synopsys

FinFET Technology – Understanding and Productizing a New Transistor From TSMC and Synopsys
This white paper discusses the major challenges with FinFETs and how TSMC has been collaborating with Synopsys, one of their ecosystem partners, to deliver a complete solution. Key elements of this solution include comprehensive FinFET profiling without impact to design tool runtime and proven, verified IP availability. The TSMC 16-nm FinFET solution will ensure mutual customers swiftly move to building the next generation SoCs.
Jason S.T. Chen, TSMC; Andy Biddle, Synopsys

The Benefits of Static Timing Analysis Based Memory Characterization
With the latest developments in STA technology, it is now possible to time not only the control logic (transistor-level digital circuits) of a memory block, but also paths through the memory core array (i.e. bit-column, wordline, column mux, sense amp, and so on). The result is an improvement in design turn-around-time, verification coverage, accuracy (within ±5% of SPICE), and productivity for designs with embedded memories.
Ken Hsieh, Product Marketing Manager, Synopsys, Inc.

Custom and Mixed-Signal Design Solution
Synopsys’ unified solution for custom and cell-based design and verification provides a comprehensive, highly integrated suite of tools for advanced-node mixed-signal SoC design. The high degree of integration and interoperability shortens time-to-tapeout and improves design quality.
Synopsys

Understand and Avoid Electromigration (EM) & IR-drop in Custom IP Blocks
This whitepaper discusses the various trends exacerbating EM and IR-drop effects as well as design and analysis techniques to avoid them, and introduce Synopsys’ transistor-level analysis solution, which includes CustomSim for FastSPICE circuit simulation, StarRC for extraction, and Galaxy Custom Designer for custom layout.
Bradley Geden, Solutions Architect, Synopsys

Boosting Designer Productivity by Using Look-ahead Constraint Analysis Technology
In this paper, we present a unique constraint analysis technology that checks for timing constraints problems and provides an interactive environment with context-sensitive diagnostic and fixing suggestions. Using this technology, design teams can save several weeks of engineering effort in a typical IC design project.
Cho Moon, R&D Manager, Synopsys George Mekhtarian, Product Marketing Manager, Synopsys

StarRC Custom Rapid3D Extraction
The next-generation Rapid3D technology in StarRC Custom provides an integrated 3D extraction solution to address these growing accuracy, performance, capacity and ease-of-use needs. This paper presents the new Rapid3D technology and the benefits it provides for a range of target applications, including IP characterization as well as custom analog/mixed-signal (AMS), high-speed digital and memory array designs.
Omar Shah CAE, Synopsys Inc. Mathew Koshy R&D Manager, Synopsys Inc.

StarRC™ Custom: Next-Generation Modeling and Extraction Solution for Custom IC Designs
Custom digital, analog/mixed-signal, and memory designs are particularly sensitive to the nanometer device parameters and parasitics. At 40-nm process technology and beyond, approximating or ignoring the new interconnect and device effects in custom designs can lead to inaccurate post-layout simulation results and jeopardize the chances of successful silicon.
Krishnakumar Sundaresan, Principal Engineer and CAE Manager, Synopsys Inc

In-Design Rail Analysis™ Accelerates Power Network Closure
In today’s complex system-on-chip (SoC) designs, static and dynamic voltage-drop and electromigration (EM) effects are increasing. At 90 nanometer (nm) and below, these effects are having a profound impact on timing, contributing 10 to 15 percent delay sensitivity and overall design viability. Due to the performance sensitivity to power and ground (P/G) noises, rail analysis solutions that have been used in high performance networking, wireless/mobile or low-power consumer applications become critical for all design applications at advanced process nodes.
Joy Han, Implementation Group, Synopsys

PrimeTime Advanced OCV Technology
An accepted trend in the semiconductor industry, where process geometry is continuously shrinking, is the growing impact of variation in static timing analysis (STA). The growing impact of variation in modern designs requires an improved OCV handling capability that takes advantage of improved device-level variation techniques. This white paper highlights the Advanced OCV solution, a sophisticated technology from PrimeTime for providing the right balance between accuracy and performance.
Sunil Walia, Product Marketing Manager, Synopsys

Extraction Techniques for High-performance, High-capacity Simulation
Today’s advanced process technologies and faster time-to-market schedules are pushing the limits of verification tools. Post-layout simulation runtimes are increasing 2-4x with every new process generation as chip transistor counts double and new parasitic effects come into play. The Synopsys StarRC™ extraction solution offers a wide range of features to boost the simulation performance and capacity of transistor-level custom digital, analog/mixed-signal and memory designs.
Omar Shah, Corporate Application Engineer; Shekhar Kapoor, Marketing Manager

Accurate Signoff Using Path Based Analysis
Path-based analysis is a feature which was introduced in PrimeTime Y-2004.06 release. This technology offers a substantial improvement in static timing analysis accuracy for both PrimeTime and PrimeTime SI. This paper looks discusses this exciting technology, explores how it is implemented and discusses how to put it to work immediately in your PrimeTime or PrimeTime SI flow.
Chris Papademetrious, Corporate Applications Engineer, Synopsys Implementation Group

Improve SoC Design Productivity By Performing Quality Checks
When combining intellectual property (IP) blocks from various sources, the chip-level implementation teams may not have the detailed IP knowledge required to develop timing constraints for the IP.
Michael Robinson, Senior Design Consultant, Synopsys Professional Services

Fixing Hold Violations Across Many Modes and Corners with DMSA
Fixing hold violations is normally a straightforward process of inserting a delay at a pin that has a negative hold slack. The challenge is choosing the amount of delay so that it improves or resolves the hold violation without incurring a setup violation. PrimeTime provides a capability called Distributed Multi-Scenario Analysis (DMSA). This capability provides a mechanism for running multiple full PrimeTime analyses while interfacing to them with a single PrimeTime control shell called the master.
Chris Papademetrious, Corporate Applications Engineer, Synopsys Implementation Group

Expanding the Synopsys PrimeTime Solution with power analysis
Design closure in today’s advanced designs requires a delicate balance of many complex issues. Timing remains critical, but power has become important toward achieving design success. Today, power management is a mainstream design challenge and a key concern for chip designers.
Gordon Yip, Product Marketing Manager, Synopsys, Inc.

Static Timing Verification of Custom Blocks Using Synopsys’ NanoTime® Tool
With the continued evolution of processes reaching levels below 90-nanometers (nm), nanometer effects are having a significant and growing impact on delay and require a number of changes in the approaches used to predict delays.
Dr. Larry G. Jones, Implementation Group, Synopsys, Inc.

Design practices and strategies for efficient signal integrity closure
The physical implementation of very deep sub-micron (VDSM) designs benefits from good, up-front planning processes, both in terms of schedule as well as quality of results. While the optimal planning strategy is design-dependent, there are a variety of design best practices that have proven successful in streamlining the physical design process.
Sachin Idgunji, Steve Lloyd, Rick Mitchell, Ron Spillman, Jon Young

Harnessing Multicore Hardware to Accelerate PrimeTime® Static Timing Analysis
In the last few years, the trend in CPU performance improvement has shifted from raw computational speed to parallelism as various memory and power (heat dissipation) limits have been reached at the higher clock frequencies. After surpassing clock speeds of 3 GHz, further CPU performance improvement is now achieved by increasing the number of computational elements (cores) within a given CPU package.
Steve Hollands, R&D Manager, Synopsys, Inc., George Mekhtarian, Product Marketing Manager, Synopsys, Inc.



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