All Synopsys News

Oct 20, 2014VIA Technologies Cuts Silicon Test Time by 11X Using Synopsys' DFTMAX Ultra
Standardizes on DFTMAX Ultra for Designs with Few Test Pins

Oct 20, 2014Synopsys Introduces Industry's First On-Chip Memory Test and Repair Solution for Embedded Flash
DesignWare STAR Memory System for Embedded Flash Reduces Test Cost by 20 Percent and Enables In-Field Diagnostics for IoT and Automotive SoCs

Sep 09, 2013DFTMAX Ultra Significantly Reduces Silicon Test Costs
Customers Realizing Up to 3x Higher Compression with Fewer Test Pins

Jun 11, 2013Synopsys Unveils New Synthesis-Based Test Technology Delivering Up to 3X Higher Compression

Sep 20, 2011Synopsys Enhances Volume Diagnostics Solution to Accelerate Yield Ramp
Innovations in TetraMAX ATPG and Yield Explorer Increase Throughput and Ease Deployment

Sep 20, 2011Synopsys' DesignWare STAR Memory System Shipped in 1 Billion Chips
Design Teams Worldwide Quickly Achieve Test and Repair Quality Goals for Embedded Memories

Nov 01, 2010Synthesis-Based Test Technology Increases Designer Productivity
Synopsys’ new test technology enables designers to achieve optimal quality-of-results and eliminate time-consuming iterations between design and test.

Oct 26, 2010Power-Aware Test Speeds Time to Volume Production at Realtek
Reducing Power Consumption and IR Drop During Manufacturing Test Enables Faster Delivery of Working Silicon

Sep 08, 2010Synopsys DFTMAX Compression Cuts Pin-Limited Test Cost by 95 Percent at Silicon Image
Using the new pin-limited test capability in Synopsys’ DFTMAX, Silicon Image designers easily implemented test compression for the mixed-signal chip in just two days, substantially reducing test time, data and cost while achieving high test coverage.

Nov 03, 2009Synopsys TetraMAX ATPG Cuts Test Development Schedule at Arrow Electronics
Multicore Processing Speeds Runtime by 3X, Accelerates Time-to-Quality

Nov 02, 2009Synopsys Extends DFTMAX Compression to Reduce the Cost of Pin-Limited Test
Delivers predictable high compression with only one pair of test data pins

Oct 28, 2009NVIDIA Adopts Synopsys Yield Explorer to Reduce Time to Volume
Design-centric yield management enables product engineers to achieve rapid yield ramp and provide cost-effective yield control in volume production

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