|Signalcrafters Achieves Design Goals and Cuts FPGA Cost by 50%|
In Signalcrafters’ first attempt to use an FPGA for DSP algorithms, their development environment kept producing erroneous results. After evaluating the other solutions available on the market, Signalcrafters found that only one — Synplify Pro® software from Synopsys — generated output that worked.
Signalcrafters Tech, Inc.
|Faraday Technology Corporation Achieves Over 50% Performance Improvement on PCIe Controller Designs with Synplify|
Faraday Technology Corporation, a leading IC design services company and intellectual property (IP) provider, had to boost performance from 80 MHz to 125 MHz on a pair of new designs for a key product line, the PCIe controller IP family. By employing the Synplify® Premier and Identify® tools from Synopsys, Faraday not only achieved its 125 MHz goal but also saved on time to market, area, and cost.
Faraday Technology Corporation
|IMEC Surpasses Critical Performance Goal for C-Programmable|
IMEC, a European nanoelectronics research institution, used Synplify® Premier software from Synopsys to demonstrate that its C-programmable reconfigurable processor architecture, ADRES, is feasible for use in portable wireless multimedia devices. The entire processor system was successfully prototyped for a multimedia ADRES processor instance on a Xilinx Virtex®-4 FPGA through use of the Synplify Premier tool.
"It is clear that for 90-nm FPGAs and beyond, the timing closure offered by the Synplify Premier tool is crucial."
Activity Leader of the Integration Team,
|SeaMicro – Synplify Pro Enables First Time Success|
We were very impressed with Synplify Pro's ability to meet all targets - area, performance and timing - on the first try. We succeeded in reducing both risk and costs for multiple designs.
VP of Hardware and System Engineering,
|STMicroelectronics – Rapid Delivery of Demodulator IP for Analog TV Standards using Synphony Model Compiler|
By using Synopsys' Synphony Model Compiler we were able to complete our entire validation effort within two weeks and with extremely reliable results.
Technical Leader IP Algorithms,
|Teradici – ASIC Prototyping Made Fast and Efficient with Synplify Premier|
Other tools can't handle the complex constructs of the ASICs we're working on. Only Synplify Premier gives us the ability to synthesize native ASIC code untouched for our FPGA prototype.
Engineering Manager, Silicon Validation Group,