Synplify Pro® FPGA synthesis software, part of the Synopsys FPGA design solution, is the industry standard for producing high-performance, cost-effective FPGA designs. Its unique Behavior Extracting Synthesis Technology® (BEST™) performs optimization at a high level first, before synthesizing the RTL code into specific FPGA logic. This approach allows for superior optimization across the FPGA, provides fast runtimes and support for very large designs.
Synplify Pro software supports the latest VHDL and Verilog language constructs including SystemVerilog and VHDL 2008. The software also supports FPGA architectures from a variety of FPGA vendors, including Altera, Lattice Semiconductor, Microsemi (formerly Actel), SiliconBlue and Xilinx, all from a single RTL and constraint source. Synplify Pro software uses a single, easy-to-use interface and has the ability to perform incremental synthesis and intuitive HDL code analysis.
For designers of large designs that need the fastest possible synthesis runtimes and the highest quality timing, area and power results. Synplify® Premier software provides all of the features of Synplify Pro as well as a comprehensive suite of tools for advanced FPGA implementation. In addition, Synplify Premier software delivers RTL compatibility between FPGA and ASIC flows, allowing designers to synthesize their ASIC RTL source files into an FPGA for FPGA-based prototyping. For a detailed comparison of the features available in each tool, see the Synplify Feature Comparison Chart.
Synplify Pro and Premier Datasheet
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- Synplify Pro logic synthesis includes:
- Incremental, block-based and bottom-up flows for consistent results from one run to the next
- Verifiable, traceable and repeatable flows for safety-critical design and DO-254 compliance
- Design for high reliability including safe finite state machines (FSMs) and control for custom error detection and mitigation
- Automatic compile points incremental flow for up to 4x faster runtime while maintaining QoR
- Scripting and Tcl/Find support for flow automation and customizable synthesis, debug and reporting
- Optimal area and timing results using FPGAs from Achronix, Altera, Lattice, Microsemi, Xilinx
- Hierarchical team design flow allowing parallel and/or geographically distributed design development
- Comprehensive language support including Verilog, VHDL, SystemVerilog, VHDL 2008 and mixed-language design
- FSM Compiler and FSM Explorer for automatic extraction and optimization of finite state machines from RTL
- Graphical state machine viewer to automatically create bubble diagrams for debugging and documenting FSMs
- Automatic memory and DSP inference provides automatic implementation of a design with optimal area, power and timing quality of results
- Incremental static timing for analysis allows updates to timing exception constraints with immediate visibility into results, without re-synthesis
- HDL Analyst interactive graphical analysis and debug tool for design diagnosis, problem isolation and functional and performance analysis