Laker Test Chip Development System 

Superior Test Chips with Less Effort 

The Laker™ Test Chip Development (TCD) system is a dedicated solution for test chip development that dramatically reduces technology time-to-market by creating reusable parameterized test structure (see Figure 1) and test line libraries. Parameterizing structures allows you to create as many layout variations from a single structure by assigning variables to key drawing dimensions. With the Laker TCD system, you are able to change from the tedious and error-prone conventional test chip development flow to an efficient, consistent, and automated methodology.

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  • Reduce test chip development cycle time from months to weeks or days vs. conventional test chip development methods
  • Reduce process development costs with fewer mask-set and wafer respins by removing the guesswork of manual test chip layout and documentation. Parameterized test line architecture provides true scalability and reusability across multiple technology nodes and process varieties.

Parameterized Test Structure
Figure 1: Parameterized Test Structure

Major Features
The Laker Test Chip Development process requires two products, Laker TestLine Manager and Laker TestLine Realizer.

Laker Test Line Manager
  1. Create parameterized test structures and devices
  2. Create parameterized testlines by defining the probe line (pad arrangement) template, placing the chosen parameterized test structures and assigning connectivity
Laker Test Line Realizer
  1. Create a split table of parameters, realize (generate the layout) and route and document the generated test lines
  2. Assign test line locations to create test chip blocks and final layout
Laker Test Line Manager
Laker Test Line Manager, which prepares parameterized test lines, consists of four major components:
  • Test Structure Compiler
  • Parameterized Test Structure Library
  • Probe Line Editor
  • Test Line Editor

Test Structure Compiler
The Test Structure Compiler (see Figure 2) is the knowledge engine that captures the “master” test structures and assigns parameters to their flexible elements, creating parameterized test structures. The test structures can be as simple as a metal plate, a Kelvin contact or a transistor, and can be as complex as a variable via chain, a differential pair or even a ring oscillator.

Test Structure Compiler
Figure 2: Test Structure Compiler

Parameterized Test Structure Libraries
Test structures are stored in the Parameterized Test Structure library, a central repository of all test chip information. A generic test structure library is supplied in the Laker TCD.

Probe Line Editor
The Probe Line Editor is an interactive graphical user interface that specifies the configuration of the probe pads. It delivers a flexible template that allows adjusting the pad alignment or creating custom pad arrangements.

Test Line Editor
Using the Test Line Editor, test lines are created by placing devices from the PTS library in the probe lines and specifying connectivity. An easy-to-use preview editor allows you to try out various combinations of probe lines and PTS.

Laker Test Line Realizer
Laker Test Line Realizer is the core of the Laker TCD system. It manages and compiles all master test lines into actual layouts and corresponding documents. The Test Line Realizer (see Figure 3) employs a specialized test chip routing algorithm, including tapered and mesh interconnects. Automated layout creation provides accuracy and quality that is significantly better than manual layout approach.

Test Line Realizer
Figure 3: Test Line Realizer

Laker Layout
Laker TCD includes much of the functionality of the Laker layout tools. The layout editor enables you to lay out specialized devices and assemble test chips with a mixture of IP, library development modules and test lines.

Document and Netlist Generator
The automated Document Generator (see Figure 4) offers a graphic notation interface that enables the user to easily document test structure parameters. At the same time, the Netlist Generator generates a netlist that enables test line LVS verification.

Document and Netlist Generator
Figure 4: Document and Netlist Generator

Supported Platforms
  • Solaris SunOS 5.7, 5.8, 5.9, 5.10 SPARC (32-bit/64-bit)
  • Linux Redhat 7.2, 8.0, 9.0 (32-bit)
  • Linux Redhat Enterprise 3.0 (32-bit/64-bit)
  • Linux Redhat Enterprise 4.0 (32-bit/64-bit)
  • HP-UX 11.0 (64-bit)

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