Model-based design environments are popular for DSP algorithm design and exploration because they allow concise representation of behavior at very high levels of abstraction. These environments provide fast design capture and easy-to-use simulation and debugging tools. However, problems arise when the designer needs to translate the DSP design intent into hardware optimized for ASIC or FPGA implementation. Hand-coding RTL for DSP algorithms is very time consuming and error prone, and requires tedious re-verification of the design in the RTL domain. Furthermore, hardware architecture exploration for area/delay/power trade-offs is limited because of these difficulties. The Synphony Model Compiler
solution addresses these problems by providing an easy and automated way to create ASIC and FPGA hardware from high-level models created in the Simulink®/MATLAB® model-based environment.