Architecture Design Models 

Pre-Instrumented for Performance Analysis in Platform Architect 
Highlights
  • Traffic Generators
  • Interconnect Models
  • Memory Subsystem Models
  • Processor Models

Synopsys Platform Architect supports the broadest commercially available portfolio of pre-instrumented SystemC TLM models for SoC architecture exploration and validation. Synopsys Architecture Design Models enable architects and system designers to efficiently design, analyze, and optimize the performance and cost of multicore SoC architectures in Platform Architect.

The library contains SystemC TLM models of commonly required architectural components including generic traffic generators, interconnects, memory subsystems, and embedded processors, including:

Traffic Generators
  • Generic File Reader Bus Master (GFRBM) for trace-driven traffic generation
  • Generic Virtual Processing Unit (VPU) for application task-mapping and task-driven traffic generation
Interconnect Models
  • Cycle-accurate SystemC TLM bus libraries for ARM AMBA® 2 AHB™/APB™, AMBA 3 AXI™, and AMBA 4 AXI™ protocols, including models for ARM CoreLink™ Network Interconnect and Synopsys DesignWare IP solutions for AMBA.
  • Generic approximately-timed SystemC TLM bus libraries for industry-standard IEEE 1666-2011 SystemC TLM-2.0 protocols, plus support for the approximately-timed models available from Arteris® for the Arteris FlexNoC™ Network on Chip (NoC) interconnect, which provide on-chip connectivity for AMBA® AXI™, AHB™, AHB-Lite, APB™, OCP and PIF protocols.
Memory Subsystem Models
  • Generic approximately-timed SystemC TLM memory subsystem models for ARM AXI and IEEE-1666 2011 SystemC TLM-2.0 interfaces
  • Cycle-accurate memory subsystem models are available for Platform Architect through HDL co-simulation with Synopsys, user-provided, and third-party RTL memory controller IP.
Processor Models
  • Cycle-accurate SystemC TLM processor support packages (PSPs) are available for Tensilica and MIPS processor families, and through HDL co-simulation with user-provided RTL for ARM processor families.

Developed in partnership with leading IP providers including ARM, Tensilica, and MIPS these models are configurable and fully instrumented for performance analysis. In addition, see the DesignWare TLM Library and Virtual Prototyping Models pages for more models that are compatible with our Architecture Design solution. Synopsys can also work with customers to create architecture performance models through our CoStart Enablement Services.


Contact us

You can find these and
many other models at TLM Central


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