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What People Are Saying

"We have adopted VCS, SystemVerilog and the VMM methodology for our next generation of advanced SoC verification environments. SystemVerilog and the VMM methodology have proven easy to adopt and deploy with the VCS solution, and will enable significant improvements in verification productivity in our Soc designs using the SuperHyway bus."

Kazunobu Morimoto
Group Manager, System Level Design and Verification Technology

"Moving to a SystemVerilog-based verification flow with VCS NTB has doubled our verification productivity compared with previous projects. The VMM methodology was of immeasurable help in getting us started with SystemVerilog and has enabled our team to build a complete, robust and scalable verification environment in just a matter of months."

Scott Scheeler
Vice President of Engineering

"The VMM methodology provides a powerful, robust and open approach to creating SystemVerilog verification environments more quickly and easily. The easy access to Synopsys' implementation of the VMM Standard Library source code has given us additional insight into the methodology and will help ensure project portability across multiple EDA tools."

Alan Sherman
Principal Member of Technical Staff

"We are taking full advantage of the VCS solution's support for the VMM methodology, the VCS Verification Library, powerful constraint solvers and integrated testbench debug environment to complete our verification tasks more productively. The VMM Methodology in particular helps us create a more consistent verification environment."

Steve Blightman
Founder and Manager of ASIC Development

"Our previous verification methodology relied heavily on the use of hand-written directed tests, followed by extensive lab debug of FPGA prototypes. For the Warp MD project, we needed a new verification methodology to handle the increased complexity of the design. We ramped up quickly on SystemVerilog with VCS NTB and used the VMM to help us create a well-structured, scalable testbench environment. The move to SystemVerilog with VCS NTB and the VMM methodology enabled our verification project to be completed a full month ahead of an already aggressive schedule. Deciding to use the VMM was the best thing we could have done."

Simon Lacroix
Hardware Developer
Ross Video Limited

"Using the new SystemVerilog constructs in VCS has been very beneficial in StarGen's exploration of switching architectures. The high-level language constructs allow me to code algorithms very quickly. Its backward compatibility with Verilog-1995 allows me to directly compare RTL from previous generations with the models for future chips. I would recommend SystemVerilog as a powerful modeling language."

Karl Meier
Principal Hardware Engineer

"We are using SystemVerilog in our current projects. SystemVerilog's features have enabled us to simplify our internal development that in turn allows us to provide greater value to our customers. Moreover, SystemVerilog is easy to adopt since the language enables us to make incremental changes to our RTL and verification and harness its powers. As an IP provider, we see much potential value with SystemVerilog being the single hardware description language that addresses the needs of both design and verification."

Ashish Dixit
Vice President of Hardware Engineering

"After a careful evaluation of available SystemVerilog testbench solutions, we decided to adopt VCS and VMM to replace our legacy testbench solution. VCS provided superior performance and language coverage, enabling us to quickly develop reusable, extensible verification environments using SystemVerilog and the VMM’s testbench building blocks such as transaction generators and configurable messaging. SystemVerilog and the VMM methodology also proved easy to learn - our team was writing production code within two weeks of getting started."     FIND OUT MORE...

Dan Abate
Principal Verification Engineer
Mercury Computer Systems, Inc.

"After evaluating other tools, we chose the VCS solution because of its leading support for verification with SystemVerilog and the high performance of its Native Testbench technology. With the VCS solution, we developed a sophisticated coverage-driven, constrained-random verification environment using SystemVerilog with just four months of effort. This helped us shorten the development cycle down to one third compared with previous projects."    FIND OUT MORE...

Sameer Goyal
Principal Engineer
Exar Corporation

"After a detailed evaluation of available verification solutions, we chose to adopt Synopsys' VCS solution with its comprehensive support for industry-standard SystemVerilog testbench automation. Our system-level verification environment, operating natively in the VCS solution with SystemVerilog, runs more than three times faster than our legacy environment based on early results. This high performance will allow us to run more verification cycles and achieve greater quality than was previously possible."

Hugues Deneux
General Manager
AMCC France

"Stretch is successfully using VCS' NTB technology to accelerate our verification performance. Now that the VCS solution includes testbench support for the industry-standard SystemVerilog language, we again expect to advance our verification testbench environment for the S5000 family of software-configurable processors."    FIND OUT MORE...

Wayne P. Heideman
Vice president of Engineering
Stretch, Inc.

"On behalf of the IEEE Std. 1800-2005 SystemVerilog Working Group, I would like to thank Synopsys and its technologists for their dedication and help in making SystemVerilog one of the most successful standards in EDA history. Synopsys' support and the expertise of its engineers made the standard come together quickly, so that design engineers can use the SystemVerilog language for their next-generation designs."    FIND OUT MORE...

Johny Srouji
IEEE 1800 SystemVerilog Working Group chairman

"The VMM for SystemVerilog is our recommended reference book to architect SystemVerilog verification environments. It defines the state-of-the-art for advanced, coverage-driven functional verification that engineers can use to increase chip development productivity and quality, and will complement the IP Functional Verification Guide being developed by the STARC IP Reuse Engineering Group."

Yoshiharu Furui
senior manager
IP Reuse Engineering Group

"The Verification Methodology Manual for SystemVerilog defines the state-of-the-art for advanced, coverage-driven functional verification that engineers can use to increase chip development productivity and quality. This verification methodology is destined to have a significant and enduring impact on the chip development process."

Tadahiko Nakamura
IP Verification SWG
STARC, Japan

"The Verification Methodology Manual for SystemVerilog is an invaluable reference for verification engineers. It enables users to elevate SystemVerilog from a collection of language constructs into a state-of-the-art methodology for coverage-driven functional verification."

Mike Benjamin
Functional Verification Group Manager
HPC IP and Design

"The Verification Methodology Manual for SystemVerilog provides an excellent, wellstructured, reuse-centric, and scalable conceptual foundation to address today's complex verification requirements, based on the SystemVerilog standard."

Dr. Wolfgang Ecker
Infineon Technologies AG

"The VMM for SystemVerilog will enable any SoC or IP development team to achieve higher levels of verification productivity and quality by providing a standard, interoperable methodology for taking advantage of the coverage-driven, constrained-random techniques used by industry experts.”    FIND OUT MORE...

Zenji Oka
Manager Electronic Devices Company

"The VMM for SystemVerilog will enable all SoC and IP project to establish an effective, predictable, and reusable verification process using SystemVerilog that is based upon the experience of leading industry experts."    FIND OUT MORE...

Yoshio Takamine
Group Manager
System Level Design and Verification Technology Development
Renesas Technology Corp.

"SystemVerilog is emerging as the hardware design and verification language of choice, but choosing the right language is only part of what is needed to develop a complete solution. The Verification Methodology Manual for SystemVerilog provides both strategies and details on how to use SystemVerilog's advanced capabilities to create efficient, modern, interoperable coverage-driven verification environments."

Michael Garcia
Design and Verification Methodology Manager
Freescale Semiconductor

"By making their implementation of the VMM Standard Library available as source code, Synopsys is providing a jump-start to designers to use the verification techniques contained within the VMM for SystemVerilog. This will enable our Partners to apply sophisticated SystemVerilog verification methodologies to their ARM® technology-based designs and will benefit other SoC designers in the electronics industry as a whole by offering a way of standardizing verification."    FIND OUT MORE...

Tim Holden
Director of EDA relations

"The Verification Methodology Manual for SystemVerilog is a blueprint for developing an effective and predictable verification strategy. It provides details and techniques on implementing advanced capabilities to build modern, interoperable coverage-driven verification environments based on SystemVerilog that enable faster and more effective verification."

Seiichi Nishio
Sr. Manager of Design Methodology
Toshiba Corporation

"We have had great success with Synopsys' Native Testbench technology, and have taken advantage of its powerful constraint solver and coverage engines to develop sophisticated and powerful verification environments. Pioneer-NTB will be especially valuable to many of our major European clients, enabling them to take advantage of SystemVerilog verification with Synopsys' Native Testbench technology running with their existing mixed-HDL simulation environments."    FIND OUT MORE...

Jason Sprott
Vice president of Consulting
Verilab, Ltd.

"We make extensive use of the VCS solution's built-in coverage features to help monitor progress to our verification plan. SystemVerilog assertions in particular have quickly become an important part of our verification and debug strategies, and are being eagerly adopted by our design teams."

Eric Costello
Design Methodology Manager
Atmel Corporation

"SystemVerilog will enable us to adopt new, but proven verification technologies to our product development with the single language. Making the most use of SVA and SVTB, we will build an efficient verification environment so that we can realize higher-quality design and a shorter development period."

Yoshio Takamine
Group Manager
System Level Design and Verification Technology Development
Renesas Technology Corp.

"Paradigm Works is engaged with helping a growing number of companies as they adopt SystemVerilog as their unified language of choice for designing and verifying complex ASICS, FPGAs, Design IP, and Verification IP. SystemVerilog's Object-Oriented nature, support of higher level verification methodologies such as constrained random and assertion based testing, and its interoperability with C and other languages make it particularly well suited to addressing their very complicated verification challenges. We see this capability coupled with its growing maturity as an advanced design language to be very compelling, and envision SystemVerilog to be an important design and verification language for the next generation of IC and systems development."

Jim Crocker
VP of Engineering & Founder
Paradigm Works