Accelerating Innovation in Memory Design  

Synopsys provides comprehensive toolsets, methodologies, and services to address your memory design requirements to decrease costs and increase yield. Synopsys design tools allow you to push the limits of line widths to create efficient bit cells and integrate cell arrays into a complete chip for manufacturing.

Synopsys Manufacturing tools help you prototype a mix of technologies and design approaches to increase yield and dramatically cut wafer test expense. Technology CAD tools (TCAD) let you explore different device technologies to create the right mix of performance, manufacturability, and cost-effectiveness.



Memories are one of the fastest growing segments, but come under enormous cost, consumer, and competitive pressures with unpredictable fluctuations in supply and demand. These pressures and market fluctuations require memory providers to be flexible and always conscious of ways to reduce costs.

Memory designs are severely cost- and area-driven. The more bit cells that can be placed on the smallest possible area, the higher the yield. However, smaller areas and line widths cause significant problems with electrical integrity and manufacturing – problems that should be addressed early in the design cycle.

Synopsys understands your need to create highly-concentrated, low-cost memory devices that provide flexible function for today’s demanding market needs. We are a technology leader in integrated circuit and SoC design and have the right tools and methodologies to deal with your cutting-edge design needs from IC Design, Verification and Manufacture. Find out how we can help you increase capacity, decrease design time, and lower production costs.

Synopsys is a world leader in electronic design with the tools and methodologies to define and optimize today’s complex memory devices. From the bit cell to the final memory array and from design to manufacture, Synopsys helps you develop the most efficient and cost-effective designs.

Design Implementation
Synopsys provides a full range of tools and methodologies to meet the complex design, compressed areas, high yields, and tight market windows of today’s competitive memory market.

Design Verification
Once design implementation is complete, the memory system must be extensively verified to ensure performance meets design specification. Verification is complicated because of the interdependencies of cell arrays, but Synopsys can help with a full line of verification tools.

Design Manufacturing
As functional integration grows at 45nm, the need for cost-effective manufacturing and yield analysis becomes crucial. Synopsys is the leader in DFM, Yield Analysis, and Technology CAD (TCAD) for advanced large-scale chip design.

  • DFM – a suite of tools incorporating design-for-manufacturing rules and best practices to reduce costs for high-volume chip design
  • Yield Analysis - estimate and improve wafer yield based on technology, materials, and processing techniques on high production chip design
  • TCAD – Technology CAD for determining cost-effective chip design to meet performance and reliability goals

Bit Cell
Memory design starts with the individual bit cell that makes up the core of the Memory device. Creating efficient cell areas is crucial in competitive market conditions. Synopsys provides leading-edge tools, IP, and services to create the most efficient and cost-effective bit cell to take advantage of constantly innovative materials and technology.

Memory Array
As the memory bit cell is being designed, other design teams are working to integrate the bit cells into the complete chip, including cell interfaces and I/O to other systems.