FinFET Solution 

 

Synopsys has a proven track record for delivering solutions targeting the most advanced process nodes. In collaboration with IDMs, foundries and academia, Synopsys has delivered a comprehensive FinFET solution.

 
  • TCAD
  • Process and device simulation tools more

Sentaurus Process
An advanced 1D, 2D and 3D process simulator for developing and optimizing silicon process technologies


Sentaurus Topography
A 2D and 3D simulator for physical modeling of topography-modifying process steps such as deposition, etching, spin-on-glass, reflow and CMP


Sentaurus Device
An advanced multidimensional (1D/2D/3D) device simulator for electrical, thermal and optical characterization of silicon-based and compound semiconductor devices


Taurus TSUPREM-4
A 1D and 2D process simulator for developing and optimizing silicon process technologies


Taurus Medici
A 2D device simulator that models the electrical, thermal and optical characteristics of semiconductor devices


HSPICE
The industry's "gold standard" for accuracy, offers foundry-certified device models with state-of-the-art simulation and analysis algorithms.
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CustomSim
High-performance, high-capacity FastSPICE simulation
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FineSim
Full-chip circuit-level simulation
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DC Explorer
Early RTL exploration to accelerate synthesis and place and route
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DC Ultra
Best-in-class timing, area and power QoR correlated with physical results
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Design Compiler Graphical
Extends topographical technology to predict & alleviate routing congestion
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Power Compiler
Provides complete solution for power synthesis & optimization PDF
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DFTMAX
Adaptive scan compression for cost-effective DSM testing
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TetraMAX ATPG
Automatic test pattern generation & diagnostics for high-quality tests
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Formality
Equivalence checking for designs synthesized with DC Ultra
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IC Compiler II
Netlist to GDSII place and route system enabling 10X faster throughput



IC Compiler
Comprehensive place and route for established and emerging process nodes
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Custom Designer SDL
Custom design schematic-driven layout
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Laker Custom Design
Custom IC design and layout solution


PrimeTime
Golden timing sign-off solution and environment
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NanoTime
Transistor-level STA for Custom Designs and Embedded Memories
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StarRC
Parasitic extraction
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Interface IP
Standard interfaces for SoC designs such as USB, PCIe, DDR, SATA, HDMI, MIPI, Ethernet and more.


Logic Libraries
Logic libraries for a wide array of applications and process technologies.


Memory Compilers
DesignWare Memory Compilers are optimized for high performance and high density with advanced power management features.


HPC Design Kit
A suite of high-speed and high-density embedded memories and logic libraries deliver optimized performance, power and area on CPU, GPU, and DSP cores.


STAR Memory System
The DesignWare STAR Memory System is a comprehensive, integrated test, repair and diagnostic solution that supports repairable and non-repairable embedded memories across any foundry or process node.

  • Broadest silicon-proven FinFET-ready EDA solution spanning Process development, SPICE design Implementation and IP
  • Earliest collaboration with foundries and academia for development of latest models and process development and certification
  • Comprehensive solution for the new challenges, such as double-patterning and 3-D transistors, introduced by 20nm planar and 16/14nm and below FinFET manufacturing rules with 3D-IC integration
  • Minimizes impact to existing methodology with transparent adoption, easing transition to advanced process technologies
  • Complete foundry-certified solutions for IC Design, Implementation and Signoff for correct first-time silicon

Design Challenges

16/14nm and below FinFET and 20nm advanced geometry nodes pose significant design and manufacturing challenges that impact some implementation tools. In particular, complex double patterning lithography requirements involve:
  • Rule-aware placement and routing to ensure ability to color masks correctly and efficiently
  • In-Design physical verification throughout the flow to reduce time-consuming, uncertain iterations
  • Accurate higher levels of extraction and timing analysis to allow for manufacturing variability

Advanced geometry nodes will enable designs to run at a multi-GHz+ operating frequency. In order to achieve this, improved modeling, guidance and analysis should be handled by the tools with high degrees of predictability throughout the design flow. Size and performance requirements for next-generation designs require higher levels of capacity, enhanced multi-core processing for faster runtime and an integrated design environment to maximize design productivity. Synopsys’ comprehensive, foundry-certified advanced geometry solution provides the following features that help designs make it to market faster:
  • Early RTL design exploration and block feasibility analysis
  • Physical guidance from synthesis to place and route
  • Digital and Custom co-design for advanced mixed-signal requirements
  • In-Design physical verification with automatic detection and repair of complex design rules
  • Tightly-coupled extraction and signoff capabilities with implementation tools
  • Physical ECO guidance and leakage recovery capabilities from signoff analysis
Foundry Partners and Consortiums

Synopsys is actively working with leading foundries, consortiums and eco-system partners to address the significant challenges of FinFET, 20nm planar CMOS and below process technologies. This results in availability of foundry certified solutions in the shortest possible time.

     
     
 



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