FinFET Technology – Understanding and Productizing a New Transistor From TSMC and Synopsys
This white paper discusses the major challenges with FinFETs and how TSMC has been collaborating with Synopsys, one of their ecosystem partners, to deliver a complete solution. Key elements of this solution include comprehensive FinFET profiling without impact to design tool runtime and proven, verified IP availability. The TSMC 16-nm FinFET solution will ensure mutual customers swiftly move to building the next generation SoCs.
Jason S.T. Chen, TSMC; Andy Biddle, Synopsys

Designing with FinFETs: The Opportunities and the Challenges
FinFET devices have a significantly more complex topology than planar FET devices. In addition, their design features and characteristics are quite different, creating many questions for designers. This paper discusses new design opportunities to optimize the design metrics of performance, power, area, cost, and time to market and the new design challenges.
Jamil Kawa, R&D Director, Synopsys

Foundation IP for 7nm FinFETs: Design and Implementation
Learn about the challenges of IP design and implementation for 7nm FinFETs. Along with the performance and area benefits that the node brings, designers must understand the significant technical challenges stemming from increasing variability associated with tighter pitches and more complex lithography steps. Design for variability and reliability considerations will require comprehensive modeling and analysis as well as advanced circuit techniques such as on chip sensing and compensation.
Jamil Kawa, Synopsys Fellow, Synopsys

Design, Test & Repair Methodology for FinFET-Based Memories
The advent of FinFET-based memories presents new memory test challenges. This white paper covers the new design complexities, defect coverage and yield challenges presented by FinFET-based memories; how to synthesize test algorithms for detection and diagnosis of FinFET specific memory defects; and how incorporating built-in self-test (BIST) infrastructures with high-efficiency test and repair capabilities can help to ensure high yield for FinFET-based memories.
Dr. Yervant Zorian, Chief Architect and Fellow, Synopsys

Meeting the USB IP Requirements of SoC Designs from 180-nm to 14/16-nm FinFET
USB’s ease-of-use and wide availability is belied by USB IP designers’ technical innovations. Without these innovations, USB could not be enabled in a broad range of process technologies ranging from 180-nm to the latest 14/16-nm FinFET technologies. This white paper addresses the five critical challenges facing designers of USB IP who need to keep pace with the process technology changes as well as the USB standard evolution.
Gervais Fong, Sr. USB Product Marketing Manager, Synopsys



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